公开(公告)号：US20130062738A1

公开(公告)日：2013-03-14

申请号：US13482020

申请日：2012-05-29

Applicant: Chung-Nan Chen

Inventor： Chung-Nan Chen

IPC: H01L29/04 ,  H01L21/306

CPC classification number: B81C1/00158 ,  B81C1/00595 ,  B81C2201/0136 ,  H05B3/141

Abstract: To form a single crystal silicon membrane with a suspension layer, a single crystal silicon substrate with crystal orientation is prepared. A doped layer is formed on the top surface of the single crystal silicon substrate. Multiple main etching windows are formed through the doped layer. A cavity is formed through the single crystal silicon substrate by anisotropic etching. The doped layer is above the cavity to form a suspension layer. If two electrode layers are formed on the two ends of the suspension layer, a micro-heater is constructed. The main etching windows extend in parallel to a crystal plane {111}. By both the single crystal structure and different impurity concentrations of the single crystal silicon substrate, the single crystal silicon substrate has a higher etch selectivity. When a large-area cavity is formed, the thickness of the suspension layer is still controllable.

Abstract translation: 为了形成具有悬浮层的单晶硅膜，制备晶体取向<111>的单晶硅衬底。 在单晶硅衬底的顶表面上形成掺杂层。 通过掺杂层形成多个主蚀刻窗口。 通过各向异性蚀刻通过单晶硅衬底形成空穴。 掺杂层在空腔之上以形成悬浮层。 如果在悬浮层的两端形成两个电极层，则构成微加热器。 主蚀刻窗平行于晶面{111}延伸。 通过单晶硅衬底的单晶结构和不同的杂质浓度，单晶硅衬底具有较高的蚀刻选择性。 当形成大面积腔时，悬浮层的厚度仍然可控。

公开(公告)号：US20120264307A1

公开(公告)日：2012-10-18

申请号：US13088106

申请日：2011-04-15

Applicant: Srivatsa G. Kundalgurki ,  James F. McHugh

Inventor： Srivatsa G. Kundalgurki ,  James F. McHugh

IPC: H01L21/302

CPC classification number: H01L21/02057 ,  B81C1/00063 ,  B81C1/00626 ,  B81C2201/0136 ,  H01L21/26506 ,  H01L21/30608 ,  H01L21/3083

Abstract: Etch stabilizing ions (37) are introduced, e.g., by ion implantation (34), into a portion (36) of a substrate (20) underlying an etch window (24) in a masking layer (22) covering the substrate (20), where a trench (26) is desired to be formed. When the portion (36) of the substrate (20) containing the etch stabilizing ions (37) is etched to form the trench (26), the etch stabilizing ions (37) are progressively released at the etch interface (28′) as etching proceeds, substantially preventing gas micro-bubbles or other reaction products at the etch interface (28′) from disrupting etching. Using this method (700), products containing trenches (26) are much more easily formed and such trenches (26) have much smoother interior surface (28).

Abstract translation: 蚀刻稳定离子（37）例如通过离子注入（34）引入覆盖衬底（20）的掩模层（22）中的蚀刻窗（24）下面的衬底（20）的部分（36） ，其中希望形成沟槽（26）。 当蚀刻包含蚀刻稳定离子（37）的衬底（20）的部分（36）以形成沟槽（26）时，蚀刻稳定离子（37）在蚀刻界面（28'）处逐渐释放，如蚀刻 进行，基本上防止蚀刻界面（28'）处的气体微气泡或其他反应产物破坏蚀刻。 使用该方法（700），包含沟槽（26）的产品更容易形成，并且这种沟槽（26）具有更平滑的内表面（28）。

公开(公告)号：US20120126346A1

公开(公告)日：2012-05-24

申请号：US13290905

申请日：2011-11-07

Applicant: Arnim Hoechst ,  Jochen Reinmuth ,  Brett Diamond

Inventor： Arnim Hoechst ,  Jochen Reinmuth ,  Brett Diamond

IPC: H01L29/84 ,  H01L21/02

CPC classification number: B81C1/00595 ,  B81B2201/0235 ,  B81B2203/0127 ,  B81B2203/0181 ,  B81B2203/053 ,  B81C2201/0112 ,  B81C2201/0133 ,  B81C2201/0136

Abstract: In a method for manufacturing a micromechanical membrane structure, a doped area is created in the front side of a silicon substrate, the depth of which doped area corresponds to the intended membrane thickness, and the lateral extent of which doped area covers at least the intended membrane surface area. In addition, in a DRIE (deep reactive ion etching) process applied to the back side of the silicon substrate, a cavity is created beneath the doped area, which DRIE process is aborted before the cavity reaches the doped area. The cavity is then deepened in a KOH etching process in which the doped substrate area functions as an etch stop, so that the doped substrate area remains as a basic membrane over the cavity.

Abstract translation: 在制造微机械膜结构的方法中，在硅衬底的前侧产生掺杂区域，其掺杂区域的深度对应于所需的膜厚度，并且其掺杂区域的横向范围至少覆盖预期的 膜表面积。 另外，在施加到硅衬底的背侧的DRIE（深反应离子蚀刻）工艺中，在掺杂区域之下产生空腔，在空腔到达掺杂区域之前DRIE工艺被中止。 然后在KOH蚀刻工艺中加深空腔，其中掺杂衬底区域用作蚀刻停止层，使得掺杂衬底区域保持为空腔上的基本膜。

公开(公告)号：US20110250397A1

公开(公告)日：2011-10-13

申请号：US12842334

申请日：2010-07-23

Applicant: Tzyy-Jiann WANG ,  Yueh-Hsun TSOU

Inventor： Tzyy-Jiann WANG ,  Yueh-Hsun TSOU

IPC: B32B3/10 ,  C23F1/02

CPC classification number: B81C1/00103 ,  B81B2203/0384 ,  B81C1/00571 ,  B81C2201/0136 ,  G02B6/12007 ,  G02B6/136 ,  G02B2006/1204 ,  G02B2006/12045 ,  Y10T428/24479

Abstract: A method of forming an undercut microstructure includes: forming an etch mask on a top surface of a substrate; forming, on a top surface of the etch mask, an ion implantation mask having a top surface that is smaller than the top surface of the etch mask and that does not extend beyond the top surface of the etch mask; ion implanting the substrate in the presence of the etch mask and the ion implantation mask so that a damaged region is generated at a depth below an area of the surface that is not masked by the ion implantation mask; and etching the surface of the substrate until the damaged region is removed.

Abstract translation: 形成底切微结构的方法包括：在衬底的顶表面上形成蚀刻掩模; 在所述蚀刻掩模的顶表面上形成具有比所述蚀刻掩模的顶表面小的顶表面并且不延伸超过所述蚀刻掩模的顶表面的离子注入掩模; 在蚀刻掩模和离子注入掩模的存在下离子注入衬底，使得在未被离子注入掩模掩蔽的表面的区域下方的深度处产生损伤区域; 并蚀刻衬底的表面直到损坏的区域被去除。

公开(公告)号：US07906439B2

公开(公告)日：2011-03-15

申请号：US12488898

申请日：2009-06-22

Applicant: François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

Inventor： François Perruchot ,  Bernard Diem ,  Vincent Larrey ,  Laurent Clavelier ,  Emmanuel Defay

IPC: H01L21/302 ,  H01L21/461

CPC classification number: B81C1/00507 ,  B81B2201/0271 ,  B81C2201/0115 ,  B81C2201/0136 ,  B81C2201/0177 ,  B81C2203/0136 ,  B81C2203/0145 ,  H03H3/0072 ,  H03H9/175 ,  H03H9/2436 ,  Y10S438/933

Abstract: The invention provides a method of fabricating and electromechanical device having an active element on at least one substrate, the method having the steps of: a) making a heterogeneous substrate having a first portion, an interface layer, and a second portion, the first portion including one or more buried zones sandwiched between first and second regions formed in a first monocrystalline material, the first region extending to the surface of the first portion, and the second region extending to the interface layer, at least one said buried zone being made at least in part out of a second monocrystalline material so as to make it selectively attackable relative to the first and second regions; b) making openings from the surface of the first portion and through the first region, which openings open out to at least one said buried zone; and c) etching at least part of at least one buried zone to form at least one cavity so as to define at least one active element that is at least a portion of the second region between said cavity and said interface layer; wherein the first and second portions of the substrate are constituted respectively from first and second substrates that are assembled together by bonding, at least one of them including at least one said interface layer over at least a fraction of its surface.

Abstract translation: 本发明提供一种在至少一个基板上具有有源元件的制造方法和机电装置，该方法具有以下步骤：a）制造具有第一部分，界面层和第二部分的非均相基底，第一部分 包括夹在形成于第一单晶材料中的第一和第二区域之间的一个或多个掩埋区域，第一区域延伸到第一部分的表面，第二区域延伸到界面层，至少一个所述掩埋区域 至少部分地由第二单晶材料制成，以使其相对于第一和第二区域选择性地具有攻击性; b）从所述第一部分的表面和所述第一区域制造开口，所述第一区域开放到至少一个所述掩埋区域; 以及c）蚀刻至少一个掩埋区域的至少一部分以形成至少一个空腔，以便限定至少一个有源元件，所述至少一个有源元件是所述腔和所述界面层之间的第二区域的至少一部分; 其中所述基板的第一和第二部分分别由通过粘接而组装在一起的第一和第二基板构成，其中至少一个在其表面的至少一部分上包括至少一个所述界面层。

公开(公告)号：US07816166B1

公开(公告)日：2010-10-19

申请号：US11716082

申请日：2007-03-09

Applicant: Emmanuel P. Quevy

Inventor： Emmanuel P. Quevy

IPC: H01L21/00

CPC classification number: B81C1/0015 ,  B81B2201/0271 ,  B81C1/00595 ,  B81C2201/0136 ,  B81C2201/014

Abstract: A method to form a MEMS structure is described. In an embodiment, a structure having a first release layer between a substrate and a member is provided. A second release layer is adjacent to a sidewall of the member. At least a portion of each of the first and the second release layers is then removed. In one embodiment, the member is formed by a damascene process. In another embodiment, the member is formed by a subtractive process. In a specific embodiment, the second release layer formed adjacent to a sidewall of the member has sub-lithographic dimensions.

Abstract translation: 描述了形成MEMS结构的方法。 在一个实施例中，提供了在基板和构件之间具有第一释放层的结构。 第二释放层与构件的侧壁相邻。 然后去除第一和第二释放层中的每一个的至少一部分。 在一个实施例中，构件通过镶嵌工艺形成。 在另一个实施例中，构件通过减法处理形成。 在具体实施例中，与构件的侧壁相邻形成的第二释放层具有亚光刻尺寸。

公开(公告)号：US07679154B2

公开(公告)日：2010-03-16

申请号：US12001289

申请日：2007-12-10

Applicant: Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Thorsten Pannek ,  Frank Schäfer

Inventor： Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Thorsten Pannek ,  Frank Schäfer

IPC: H01L29/84

CPC classification number: B81C1/00182 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0136 ,  G01L9/0042

Abstract: In a method for manufacturing a semiconductor component having a semiconductor substrate, a flat, porous diaphragm layer and a cavity underneath the porous diaphragm layer are produced to form unsupported structures for a component. In a first approach, the semiconductor substrate may receive a doping in the diaphragm region that is different from that of the cavity. This permits different pore sizes and/or porosities to be produced, which is used in producing the cavity for improved etching gas transport. Also, mesopores may be produced in the diaphragm region and nanopores may be produced as an auxiliary structure in what is to become the cavity region.

Abstract translation: 在制造具有半导体衬底的半导体部件的方法中，制造平坦的多孔隔膜层和多孔隔膜层下方的空腔，以形成用于部件的无支撑结构。 在第一种方法中，半导体衬底可以在膜片区域中接收不同于空腔的掺杂。 这允许产生不同的孔径和/或孔隙率，其用于制造用于改善蚀刻气体输送的空腔。 此外，可以在隔膜区域中产生介孔，并且可以在将要成为空腔区域的地方制造纳米孔作为辅助结构。

公开(公告)号：US07494839B2

公开(公告)日：2009-02-24

申请号：US11011888

申请日：2004-12-13

Applicant: Hubert Benzel ,  Frank Schaefer ,  Simon Armbruster ,  Gerhard Lammel ,  Christoph Schelling ,  Joerg Brasas

Inventor： Hubert Benzel ,  Frank Schaefer ,  Simon Armbruster ,  Gerhard Lammel ,  Christoph Schelling ,  Joerg Brasas

IPC: H01L21/00

CPC classification number: B81C1/00158 ,  B81B3/007 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0116 ,  B81C2201/0136

Abstract: A manufacturing method for a micromechanical semiconductor element includes providing on a semiconductor substrate a patterned stabilizing element having at least one opening. The opening is arranged such that it allows access to a first region in the semiconductor substrate, the first region having a first doping. Furthermore, a selective removal of at least a portion of the semiconductor material having the first doping out of the first region of the semiconductor substrate is provided. In addition, a membrane is produced above the first region using a first epitaxy layer applied on the stabilizing element. In a further method step, at least a portion of the first region is used to produce a cavity underneath the stabilizing element. In this manner, the present invention provides for the production of the patterned stabilizing element by means of a second epitaxy layer, which is applied on the semiconductor substrate.

Abstract translation: 微机电半导体元件的制造方法包括在半导体衬底上提供具有至少一个开口的图案化稳定元件。 开口被布置成使得其允许接近半导体衬底中的第一区域，第一区域具有第一掺杂。 此外，提供了选择性地去除半导体衬底的第一区域中具有第一掺杂的半导体材料的至少一部分。 此外，使用施加在稳定元件上的第一外延层，在第一区域上方产生膜。 在另一方法步骤中，第一区域的至少一部分用于在稳定元件下方产生空腔。 以这种方式，本发明提供了通过施加在半导体衬底上的第二外延层来生产图案化的稳定元件。

公开(公告)号：US20070137989A1

公开(公告)日：2007-06-21

申请号：US10583719

申请日：2004-12-23

Applicant: Claire Divoux ,  Marie-Helene Vaudaine ,  Thierry Enot

Inventor： Claire Divoux ,  Marie-Helene Vaudaine ,  Thierry Enot

IPC: H01H13/72

CPC classification number: G02B26/085 ,  B81B2201/038 ,  B81B2201/047 ,  B81B2203/0127 ,  B81B2203/0361 ,  B81C1/00626 ,  B81C2201/0136 ,  G02B26/0833 ,  G02B26/0841 ,  Y10S29/016 ,  Y10S438/924 ,  Y10T29/42

Abstract: The invention relates to a method for making an actuation system for an optical component comprising: etching of a first face of a component, to form pads on it, etching of a second face of the component, to expose a membrane made of the same material as the pads, production of the actuation means of the pads and the membrane.

Abstract translation: 本发明涉及一种用于制造光学部件的致动系统的方法，包括：蚀刻部件的第一面，在其上形成焊盘，蚀刻部件的第二面，暴露由相同材料制成的膜 作为垫，制造垫和膜的致动装置。

公开(公告)号：US06658728B2

公开(公告)日：2003-12-09

申请号：US09917572

申请日：2001-07-27

Applicant: David Kirtland Fork ,  Jackson Ho ,  Rachel King-ha Lau ,  JengPing Lu

Inventor： David Kirtland Fork ,  Jackson Ho ,  Rachel King-ha Lau ,  JengPing Lu

IPC: H05K330

CPC classification number: G01R1/06716 ,  B81B2203/0118 ,  B81C1/00484 ,  B81C2201/0136 ,  B81C2203/058 ,  G01R1/06727 ,  G01R1/07342 ,  G01R3/00 ,  H01L23/49811 ,  H01L2924/0002 ,  H01R4/48 ,  H01R12/57 ,  H05K3/4092 ,  Y10T29/4913 ,  Y10T29/49135 ,  Y10T29/4914 ,  H01L2924/00

Abstract: Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad/via.

Abstract translation: 通过使用单个掩模通过形成弹簧金属和释放材料层来将含有接触垫或金属通孔的弹性结构光刻制造到衬底上的有效方法。 具体地说，使用光致抗蚀剂掩模或电镀金属图案或使用剥离处理技术，释放材料垫与弹簧金属手指自对准。 然后使用释放掩模释放弹簧金属指，同时保持将弹簧金属指的锚固部分固定到基底的释放材料的一部分。 当释放材料是导电的（例如钛）时，该释放材料部分直接位于接触垫或金属通孔上方，并且用作在完成的弹簧结构中的弹簧金属指的导管。 当释放材料不导电时，形成金属带以将弹簧金属手指连接到接触垫/通孔。