公开(公告)号：US20130232383A1

公开(公告)日：2013-09-05

申请号：US13856485

申请日：2013-04-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiromichi YAMADA ,  Kotaro SHIMAMURA ,  Kesami HAGIWARA ,  Yoshikazu KIYOSHIGE ,  Yuichi ISHIGURO

IPC: G06F11/16

CPC classification number: G06F11/1608 ,  G06F11/004 ,  G06F11/1641 ,  G06F11/1687 ,  G06F2201/83 ,  G06F2201/845

Abstract: A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.

Abstract translation: 一种微控制器，其能够通过由多个CPU执行不同的程序来提高处理性能，并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。 提供了包括CPU和存储器在内的多个处理系统，每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。 压缩存储数据由比较器相互比较，当比较结果表示不匹配时，可以检测出异常处理。 即使当多个CPU异步地执行相同的处理时，获得相同处理结果的定时也是不同的，因此可以容易地将它们的处理结果彼此进行比较，因为压缩是由压缩器执行的。 此外，由于在从所有CPU给出比较使能时能够进行比较器的比较，所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。

公开(公告)号：US08527681B2

公开(公告)日：2013-09-03

申请号：US12599994

申请日：2007-05-25

Applicant: Florian Bogenberger ,  Joachim Kruecken ,  Christopher Temple

Inventor： Florian Bogenberger ,  Joachim Kruecken ,  Christopher Temple

IPC: G06F13/00 ,  G06F3/00 ,  G06F11/00

CPC classification number: G06F11/1641 ,  G06F11/1487 ,  G06F11/1675 ,  G06F15/7842 ,  G06F2201/845

Abstract: A data processing system may include a first data path and a second data path. A set of components may include a system component and a partner component, each having a communication interface for communicating data. The components are operable in a synchronized mode and a non-synchronized mode with respect to each other. The set may further include a configuration control system connected to the system component and the partner component, for controlling the set to be in a synchronized mode configuration or a non-synchronized mode configuration. The configuration control system may include a first path selector module connecting the communication interface of the system component to the first data path and the second data path and a partner path selector module connecting the communication interface of the partner component to the first data path and the second data path. The path selector modules may be arranged to enable, depending on the configuration, communication of data to the respective component via one or more selected data path, selected from the first data path and the second data path, and to inhibit communication via the not selected data paths.

Abstract translation: 数据处理系统可以包括第一数据路径和第二数据路径。 一组组件可以包括系统组件和伙伴组件，每个组件具有用于传送数据的通信接口。 组件可以相对于彼此以同步模式和非同步模式操作。 该集合还可以包括连接到系统组件和伙伴组件的配置控制系统，用于将组控制为同步模式配置或非同步模式配置。 配置控制系统可以包括将系统组件的通信接口连接到第一数据路径和第二数据路径的第一路径选择器模块和将伙伴组件的通信接口连接到第一数据路径的伙伴路径选择器模块， 第二条数据路径。 路径选择器模块可以被布置成使得根据配置能够经由从第一数据路径和第二数据路径选择的一个或多个所选择的数据路径将数据传送到相应的组件，并且通过未选择的方式禁止通信 数据路径。

公开(公告)号：US08458516B2

公开(公告)日：2013-06-04

申请号：US12656013

申请日：2010-01-13

Applicant: Hideki Matsuyama

Inventor： Hideki Matsuyama

IPC: G06F11/00 ,  G06F11/16

CPC classification number: G06F11/1658 ,  G06F9/30189 ,  G06F9/3885 ,  G06F11/1641 ,  G06F11/1679 ,  G06F2201/845

Abstract: A processor system according to an exemplary aspect of the present invention includes a first processor, a second processor, a control unit, a signal line group, and a selection circuit. The control unit switches an operation mode between a lock step mode for the first and second processors to execute the same instruction stream and a free step mode for the first and second processors to execute different instruction streams. The signal line group includes at least one signal line disposed between a first memory circuit included in the first processor and a second memory circuit included in the second processor. The signal line group is capable of transferring a storage state of the first memory circuit to the second memory circuit. The selection circuit is capable of switching a connection destination of the second memory circuit between the second processor and the signal line group.

Abstract translation: 根据本发明的示例性方面的处理器系统包括第一处理器，第二处理器，控制单元，信号线组和选择电路。 控制单元在第一和第二处理器的锁定步骤模式之间切换操作模式以执行相同的指令流以及第一和第二处理器执行不同指令流的空闲步骤模式。 信号线组包括布置在包括在第一处理器中的第一存储器电路和包括在第二处理器中的第二存储器电路之间的至少一个信号线。 信号线组能够将第一存储器电路的存储状态传送到第二存储器电路。 选择电路能够在第二处理器和信号线组之间切换第二存储器电路的连接目的地。

公开(公告)号：US20120272007A1

公开(公告)日：2012-10-25

申请号：US13090057

申请日：2011-04-19

Applicant: William C. Moyer

Inventor： William C. Moyer

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F11/1629 ,  G06F11/1658 ,  G06F12/0815 ,  G06F12/126 ,  G06F2201/845 ,  G06F2212/1016

Abstract: Cache storage may be partitioned in a manner that dedicates a first portion of the cache to lockstep mode execution, while providing a second (or remaining) portion for non-lockstep execution mode(s). For example, in embodiments that employ cache storage organized as a set associative cache, partition may be achieved by reserving a subset of the ways in the cache for use when operating in lockstep mode. Some or all of the remaining ways are available for use when operating in non-lockstep execution mode(s). In some embodiments, a subset of the cache sets, rather than cache ways, may be reserved in a like manner, though for concreteness, much of the description that follows emphasizes way-partitioned embodiments.

Abstract translation: 高速缓存存储器可以以专用于高速缓存的第一部分以锁定模式执行的方式进行分区，同时为非锁步执行模式提供第二（或剩余）部分。 例如，在使用被组织为集合关联高速缓存的高速缓存存储器的实施例中，可以通过在高速缓存中保留用于在锁步模式下操作时使用的方式的子集来实现分区。 当在非锁步执行模式下运行时，部分或全部剩余方式可用。 在一些实施例中，高速缓存集的子集而不是缓存方式可以以类似的方式保留，但是为了具体性，下面的大部分描述强调了方式划分的实施例。

公开(公告)号：US20120210172A1

公开(公告)日：2012-08-16

申请号：US13027882

申请日：2011-02-15

Applicant: Alan Gara ,  Michael Karl Gschwind ,  Valentina Salapura

Inventor： Alan Gara ,  Michael Karl Gschwind ,  Valentina Salapura

IPC: G06F11/07

CPC classification number: G06F11/1641 ,  G06F11/1654 ,  G06F2201/845

Abstract: System, method and computer program product for a multiprocessing system to offer selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). Each paired microprocessor or processor cores that provide one highly reliable thread for high-reliability connect with a system components such as a memory “nest” (or memory hierarchy), an optional system controller, and optional interrupt controller, optional I/O or peripheral devices, etc. The memory nest is attached to a selective pairing facility via a switch or a bus.

Abstract translation: 用于多处理系统的系统，方法和计算机程序产品，以提供处理器核心的选择性配对，以提高处理可靠性。 提供选择性配对设施，其选择性地连接，即配对多个微处理器或处理器核，以提供一个高度可靠的线程（或线程组）。 每个成对的微处理器或处理器核心提供一个高度可靠的线程，用于高可靠性与诸如存储器“嵌套”（或存储器层级），可选系统控制器和可选中断控制器的系统组件连接，可选的I / O或外设 设备等。存储器套件通过开关或总线连接到选择性配对设施。

公开(公告)号：US20120210164A1

公开(公告)日：2012-08-16

申请号：US13027960

申请日：2011-02-15

Applicant: Alan Gara ,  Michael Karl Gschwind ,  Valentina Salapura

Inventor： Alan Gara ,  Michael Karl Gschwind ,  Valentina Salapura

IPC: G06F11/07

CPC classification number: G06F11/1641 ,  G06F11/165 ,  G06F2201/845

Abstract: System, method and computer program product for scheduling threads in a multiprocessing system with selective pairing of processor cores for increased processing reliability. A selective pairing facility is provided that selectively connects, i.e., pairs, multiple microprocessor or processor cores to provide one highly reliable thread (or thread group). The method configures the selective pairing facility to use checking provide one highly reliable thread for high-reliability and allocate threads to corresponding processor cores indicating need for hardware checking. The method configures the selective pairing facility to provide multiple independent cores and allocate threads to corresponding processor cores indicating inherent resilience.

Abstract translation: 用于在具有选择性配对处理器核心的多处理系统中调度线程的系统，方法和计算机程序产品，用于提高处理可靠性。 提供选择性配对设施，其选择性地连接，即配对多个微处理器或处理器核，以提供一个高度可靠的线程（或线程组）。 该方法配置选择性配对设施以使用检查提供一个高度可靠的线程以实现高可靠性，并将线程分配给相应的处理器核心，指示需要进行硬件检查。 该方法配置选择性配对工具以提供多个独立核心，并将线程分配给相应的处理器核心，指示固有的弹性。

公开(公告)号：US20120192007A1

公开(公告)日：2012-07-26

申请号：US13013436

申请日：2011-01-25

Applicant: Wayne R. Weilnau, JR. ,  Elie J. Jreij

Inventor： Wayne R. Weilnau, JR. ,  Elie J. Jreij

IPC: G06F11/20

CPC classification number: G06F1/30 ,  G06F1/3234 ,  G06F1/3287 ,  G06F11/2015 ,  G06F2201/845

Abstract: A server chassis includes an uninterruptible power supply, and a server including a controller. The uninterruptible power supply is configured to provide a reserve power when a primary power is lost, and to send a power loss signal when the primary power is lost. The controller is configured to receive a desired server uptime, to receive an indication that a power limit for the server is fixed or decreasing over the desired server, to receive the power loss signal from the uninterruptible power supply, to send a power capacity query to the uninterruptible power supply, to receive a reserve power capacity of the uninterruptible power supply in response to the power capacity query, to calculate the power limit for the server based on the reserve power capacity of the uninterruptible power supply and on the desired server uptime, and to enforce the power limit on the server.

Abstract translation: 服务器机箱包括不间断电源以及包括控制器的服务器。 不间断电源被配置为在主电源丢失时提供备用电力，并且在主电源丢失时发送功率损失信号。 控制器被配置为接收期望的服务器正常运行时间，以接收指示服务器的功率限制在期望的服务器上固定或减小，以从不间断电源接收功率损耗信号，以将功率容量查询发送到 不间断电源，为了响应于电力容量查询而接收不间断电源的备用电力容量，基于不间断电源的备用电力容量和期望的服务器正常运行时间来计算服务器的功率限制， 并强制执行服务器的电源限制。

公开(公告)号：US20120185628A1

公开(公告)日：2012-07-19

申请号：US13008082

申请日：2011-01-18

Applicant: Alexandre Pierre Palus

Inventor： Alexandre Pierre Palus

IPC: G06F13/24 ,  G06F1/12

CPC classification number: G06F9/44505 ,  G06F9/38 ,  G06F9/3861 ,  G06F11/1641 ,  G06F11/1658 ,  G06F11/1675 ,  G06F13/24 ,  G06F2201/845

Abstract: An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate.

Abstract translation: 本发明的实施例提供了一种在系统继续运行软件时将多处理器系统从性能模式改变为安全模式的方法。 当外部事件或异常发生时，上下文从性能模式切换到安全模式。 在上下文切换之后，至少一对CPU被同步以在安全模式下操作。 此外，当软件继续运行时，多处理器系统可以从安全模式切换到性能模式。

公开(公告)号：US08108716B2

公开(公告)日：2012-01-31

申请号：US11990097

申请日：2006-07-27

Applicant: Eberhard Boehl ,  Juergen Sauler ,  Reinhard Weiberle ,  Bernd Mueller ,  Yorck von Collani ,  Rainer Gmehlich

Inventor： Eberhard Boehl ,  Juergen Sauler ,  Reinhard Weiberle ,  Bernd Mueller ,  Yorck von Collani ,  Rainer Gmehlich

IPC: G06F11/00

CPC classification number: G06F11/3065 ,  G05B9/03 ,  G06F11/1641 ,  G06F2201/845

Abstract: A method and device for monitoring functions of a computer system having at least two execution units, a switchover unit being provided, and switchover operations being carried out between at least two operating modes, and a comparison unit being provided, a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode, and a first function being monitored by a second function, the second function being executed in the comparison mode on at least two execution units, and each of these two second functions, which are executed on at least two execution units, monitoring the same first function.

Abstract translation: 一种用于监视具有至少两个执行单元的计算机系统的功能的方法和装置，提供了切换单元，以及在至少两个操作模式之间执行切换操作以及提供比较单元，第一操作模式对应于 对应于演奏模式的比较模式和第二操作模式，以及由第二功能监视的第一功能，所述第二功能在比较模式中在至少两个执行单元上执行，并且这两个第二功能中的每一个 在至少两个执行单元上执行，监视相同的第一功能。

公开(公告)号：US20110283033A1

公开(公告)日：2011-11-17

申请号：US13106788

申请日：2011-05-12

Applicant: Hiromichi YAMADA ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

Inventor： Hiromichi YAMADA ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

IPC: G06F13/24 ,  G06F13/26

CPC classification number: G06F13/24 ,  G06F11/1641 ,  G06F2201/845

Abstract: A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.

Abstract translation: 提供了一种缩短CPU的待机时间并提高从性能模式（并行操作）切换到安全模式（主/检测器操作）时的CPU处理效率的计算机系统。 在一个计算机系统中，包括：至少两个CPU; 用于中断CPU的可编程中断控制器; 以及比较器，用于相互比较CPU的输出，分别由CPU执行相互不同的处理的性能模式之间进行切换，以提高CPU的性能和执行相同处理的安全模式，并将比较器的结果进行比较 检测失败可以进行; 可以为每个中断因子设置要中断的CPU; 并且可以针对每个中断因子来设置执行性能模式还是执行安全模式。