公开(公告)号：US20190220393A1

公开(公告)日：2019-07-18

申请号：US16036473

申请日：2018-07-16

Applicant: SK hynix Inc.

Inventor： Jeen PARK

IPC: G06F12/02 ,  G06F13/16 ,  G06F12/06 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0673 ,  G06F12/0646 ,  G06F13/1668 ,  G06F2212/1016 ,  G06F2212/7201

Abstract: A memory system includes a memory device including first and second memory blocks, a cache read mode setting unit suitable for determining a memory block to store and manage map data for user data among the first memory block and the second memory block, and a controller suitable for performing a read operation on the user data and the map data and an update operation on the map data in parallel.

公开(公告)号：US20190220197A1

公开(公告)日：2019-07-18

申请号：US16364280

申请日：2019-03-26

Applicant: Toshiba Memory Corporation

Inventor： Hirokuni YANO ,  Shinichi KANNO ,  Toshikatsu HIDA ,  Hidenori MATSUZAKI ,  Kazuya KITSUNAI ,  Shigehiro ASANO

IPC: G06F3/06 ,  G06F12/02 ,  G11C11/56

CPC classification number: G06F3/0604 ,  G06F3/0616 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203 ,  G06F2212/7209 ,  G11C11/5628

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

公开(公告)号：US20190213137A1

公开(公告)日：2019-07-11

申请号：US16022714

申请日：2018-06-29

Applicant: Silicon Motion Inc.

Inventor： Chien-Cheng Lin ,  Chia-Chi Liang ,  Jie-Hao Lee

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F2212/1044 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: The present invention provides a method for managing a flash memory module, wherein the method comprises: reading a logical address to physical address (L2P) mapping table from the flash memory module; compressing the L2P mapping table to generate a compressed mapping table, wherein the compressed mapping table records a reference physical address and whether a corresponding physical address of each logical address is the reference physical address plus an offset value; and when receiving a read command asking for reading data corresponding to a specific logical address, referring to the compressed mapping table to determine a specific physical address corresponding to the specific logical address, and reading the data from the flash memory module according to the specific physical address.

公开(公告)号：US20190205258A1

公开(公告)日：2019-07-04

申请号：US15857857

申请日：2017-12-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Ho PARK ,  Sungkug CHO ,  Byoung Young AHN

IPC: G06F12/1009 ,  G06F12/02

CPC classification number: G06F12/1009 ,  G06F12/0246 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: A storage device includes a controller that receives a value corresponding to data stored in a memory and a key to be referenced to identify the value from a host. In addition, the controller manages partial key-value mapping information indicating a correspondence relationship between a partial key and a value address, and returns information to the host in response to a host request. The information corresponds to a key that includes a same character as a character at a specific position of the received key. The controller to determine the information by determining a partial region of the memory that stores the data based on the partial key-value mapping information and performing a read operation on the partial region to obtain an entire key including the partial key.

公开(公告)号：US20190205067A1

公开(公告)日：2019-07-04

申请号：US16294565

申请日：2019-03-06

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Daisuke HASHIMOTO ,  Shinichi KANNO

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0679 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0652 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/1016 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7209

Abstract: A storage device includes a non-volatile semiconductor storage device including a plurality of physical blocks, and a controller. The controller is configured to maintain a mapping of logical addresses to locations within the physical blocks, send, to a host, a first list that contains logical addresses corresponding to one or more target physical block that are targeted for garbage collection, and then receive, from the host, a second list that contains one or more logical addresses in the first list, and invalidate data stored in the logical addresses in the second list prior to the garbage collection.

公开(公告)号：US20190196713A9

公开(公告)日：2019-06-27

申请号：US15499877

申请日：2017-04-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jingpei YANG ,  Changho CHOI ,  Rajinikanth PANDURANGAN ,  Vijay BALAKRISHNAN ,  Ramaraj PANDIAN

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0611 ,  G06F3/0655 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F13/18 ,  G06F2212/1016 ,  G06F2212/1036 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7205

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include flash memory to store data and may support a plurality of device streams. A SSD controller may manage reading and writing data to the flash memory, and may store a submission queue and a chunk-to-stream mapper. A flash translation layer may include a receiver to receive a write command, an LBA mapper to map an LBA to a chunk identifier (ID), stream selection logic to select a stream ID based on the chunk ID, a stream ID adder to add the stream ID to the write command, a queuer to place the chunk ID in the submission queue, and background logic to update the chunk-to-stream mapper after the chunk ID is removed from the submission queue.

公开(公告)号：US20190155531A1

公开(公告)日：2019-05-23

申请号：US16260142

申请日：2019-01-29

Applicant: Silicon Motion Inc.

Inventor： Tsung-Chieh Yang ,  Chun-Chieh Kuo ,  Ching-Hui Lin ,  Yang-Chih Shen

IPC: G06F3/06 ,  G11C11/56 ,  G06F12/02

CPC classification number: G06F3/0634 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7206 ,  G11C11/5628 ,  G11C11/5642 ,  Y02D10/13

Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.

公开(公告)号：US20190138341A1

公开(公告)日：2019-05-09

申请号：US16185833

申请日：2018-11-09

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Kwang Won KOH ,  Kang Ho KIM

IPC: G06F9/455 ,  G06F12/109 ,  G06F12/02

CPC classification number: G06F9/45558 ,  G06F12/0246 ,  G06F12/109 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2212/1016 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/7201

Abstract: The preset specification provides a method of managing a disaggregated memory in a virtual system. Herein, the disaggregated memory managing method includes: detecting a memory access pattern in a virtual machine node based on an operation of a virtual machine; and performing a memory operation by using a memory block in consideration of the memory access pattern, wherein the memory access pattern is variably set based on a time at which the operation of the virtual machine is performed, and the memory block dynamically changes in size based on the memory access pattern.

公开(公告)号：US20190108136A1

公开(公告)日：2019-04-11

申请号：US16054495

申请日：2018-08-03

Applicant: SK hynix Inc.

Inventor： JongJu PARK

IPC: G06F12/121 ,  G06F12/0871 ,  G06F12/0873 ,  G06F12/02

CPC classification number: G06F12/121 ,  G06F12/0246 ,  G06F12/0871 ,  G06F12/0873 ,  G06F12/126 ,  G06F2212/7201

Abstract: A memory system includes a nonvolatile memory device including a plurality of memory blocks; and a controller including a command queue adapted to store a plurality of commands from the host, wherein the controller is suitable for managing mapping information for mapping logical addresses of the commands to physical addresses of the nonvolatile memory device, storing partial mapping information into an internal cache memory, storing the whole mapping information into the memory blocks, selecting a piece of victim mapping information among the partial mapping information stored in the internal cache memory, and removing the piece of victim mapping information based on logical addresses of the commands stored in the command queue.

公开(公告)号：US20190108120A1

公开(公告)日：2019-04-11

申请号：US16210826

申请日：2018-12-05

Applicant: Toshiba Memory Corporation

Inventor： Shinichi KANNO

IPC: G06F12/02 ,  G06F12/1009 ,  G06F3/06

CPC classification number: G06F12/0246 ,  G06F3/0616 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0679 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks and a controller. The controller manages a garbage collection count for each of blocks containing data written by a host, the garbage collection count indicating the number of times the data in said each of the blocks has been copied by a garbage collection operation of the nonvolatile memory. The controller selects, as garbage collection target blocks, first blocks associated with a same garbage collection count. The controller copies valid data in the first blocks to a copy destination free block. The controller sets, as a garbage collection count of the copy destination free block, a value obtained by adding one to a garbage collection count of the first blocks.