公开(公告)号：US06448646B1

公开(公告)日：2002-09-10

申请号：US09656762

申请日：2000-09-07

Applicant: Makoto Kitano ,  Michiharu Honda

Inventor： Makoto Kitano ,  Michiharu Honda

IPC: H01L2158

CPC classification number: H01L23/49816 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2924/15311 ,  H05K1/0269 ,  H05K3/3436 ,  H05K2201/0116 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device-mounting construction including a semiconductor device having a plurality of electrodes formed on one main surface thereof. A printed circuit board having a writing pattern formed on one main surface thereof and a plurality of solder bumps interposed between the plurality of electrodes and the writing pattern to electrically connect the semiconductor device and the printed circuit board together. All of the voids, which are present in an interface of each of those of the plurality of solder bumps which are disposed closest to an outer peripheral edge of the semiconductor device, joined to the semiconductor device, are fine, and generally uniform in size.

Abstract translation: 一种半导体器件安装结构，包括在其一个主表面上形成有多个电极的半导体器件。 一种具有形成在其一个主表面上的书写图案的印刷电路板和插在所述多个电极之间的多个焊料凸块和所述书写图案，以将所述半导体器件和所述印刷电路板电连接在一起。 存在于与半导体器件最靠近半导体器件的外周边缘配置的多个焊料凸块中的每一个的界面中的所有空隙均良好，并且尺寸基本一致。

公开(公告)号：US20020053465A1

公开(公告)日：2002-05-09

申请号：US09956205

申请日：2001-09-18

Applicant: Matsushita electric Inductrial Co., Ltd.

Inventor： Yoshihiro Kawakita ,  Daizo Andoh ,  Fumio Echigo ,  Tadashi Nakamura

IPC: H05K001/03

CPC classification number: H05K3/4626 ,  H05K1/036 ,  H05K1/0366 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4658 ,  H05K2201/0116 ,  H05K2201/0195 ,  H05K2201/0278 ,  H05K2201/0293 ,  H05K2201/0355 ,  H05K2203/0191 ,  H05K2203/1461 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/249953 ,  Y10T428/249996

Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle. Thereby, it is possible to make the insulating layer of the circuit board securing the interlayer electrically connection by an inner via hole including a conductive paste to be homogenized and ultra-thin and improve the reliability of the connection of the inner via hole.

Abstract translation: 包括所需数量的电绝缘层和交替层叠的布线层的电路板，以及用于通过压缩和硬化包括导电颗粒和树脂的导电膏来固定布线层之间的电连接的内通孔。 在电绝缘层中，多孔片材至少在一个表面上设置有树脂片，多孔片材至少在中心部分不浸渍树脂。 在电绝缘层的厚度方向贯通电绝缘层的贯通孔填充有包含导电性粒子和树脂的导电性糊剂，并且在多孔质片材内存在的孔填充有层叠树脂。 多孔片内的孔的平均孔径可以小于导电性粒子的平均粒径。 由此，可以使电路基板的绝缘层通过包含导电性糊剂的内部通路孔进行层间电连接，使其均匀化，超薄化，提高内部通孔连接的可靠性。

公开(公告)号：US20010044999A1

公开(公告)日：2001-11-29

申请号：US09803440

申请日：2001-03-09

Applicant: CoorsTek, Inc.

Inventor： Marcus A. Ritland ,  Dennis W. Readey ,  Richard N. Kleiner ,  Jack D. Sibold ,  Kyle Knudson ,  Steven Landin ,  Paul Thoen

IPC: B01D035/00 ,  B23K031/02 ,  B23P025/00 ,  B23K001/19 ,  B23K13/16 ,  B23P017/00 ,  B22D019/04 ,  B23P017/02

CPC classification number: B23K1/19 ,  B01D29/111 ,  B01D29/31 ,  B01D29/35 ,  B01D29/52 ,  B01D46/0001 ,  B01D46/2418 ,  B01D53/02 ,  B01D53/0407 ,  B01D63/061 ,  B01D63/066 ,  B01D65/003 ,  B01D2046/2433 ,  B01D2046/2437 ,  B01D2046/2481 ,  B01D2046/2488 ,  B01D2201/0446 ,  B01D2201/34 ,  B01D2201/403 ,  B01D2201/46 ,  B01D2253/104 ,  B01D2253/106 ,  B01D2253/1124 ,  B01D2253/25 ,  B01D2253/308 ,  B01D2253/311 ,  B01D2271/025 ,  B23K2103/16 ,  B32B18/00 ,  C04B37/001 ,  C04B37/026 ,  C04B41/009 ,  C04B41/5127 ,  C04B41/5144 ,  C04B41/52 ,  C04B41/88 ,  C04B41/89 ,  C04B2111/00793 ,  C04B2237/121 ,  C04B2237/123 ,  C04B2237/124 ,  C04B2237/125 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/346 ,  C04B2237/348 ,  C04B2237/36 ,  C04B2237/365 ,  C04B2237/366 ,  C04B2237/368 ,  C04B2237/406 ,  C04B2237/61 ,  C04B2237/62 ,  C04B2237/68 ,  C04B2237/708 ,  C04B2237/72 ,  C04B2237/765 ,  C04B2237/78 ,  C04B2237/80 ,  C04B2237/84 ,  C22C1/1015 ,  C22C1/1036 ,  C22C29/12 ,  C22C2001/1063 ,  F01L3/02 ,  F01L3/22 ,  F01L2101/02 ,  F02B3/06 ,  F02F3/00 ,  F02F7/0087 ,  F05C2201/0415 ,  F05C2203/0895 ,  F05C2253/16 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/5384 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/4061 ,  H05K2201/0116 ,  H05K2203/128 ,  Y10S228/903 ,  Y10T29/49885 ,  Y10T29/49982 ,  Y10T29/49988 ,  C04B41/4523 ,  C04B41/4572 ,  C04B41/4582 ,  C04B41/5093 ,  C04B41/5133 ,  C04B35/10 ,  C04B38/0003 ,  H01L2924/00

Abstract: A process for sealing a ceramic filter by infiltrating a metal into an end of the filter. The process includes the steps of contacting the end of a porous ceramic filter with a molten metal, whereby the metal enters into the ceramic matrix to substantially fill the void space. The ceramic filter is cooled to form a filter having a ceramic-metal composite portion. The present invention also provides a filter having an infiltrated metal seal. Methods for joining infiltrated ends are also provided.

公开(公告)号：US06211487B1

公开(公告)日：2001-04-03

申请号：US09379008

申请日：1999-08-23

Applicant: Akihito Hatakeyama ,  Seiichi Nakatani ,  Kouji Kawakita ,  Hiroshi Sogou ,  Tatsuo Ogawa ,  Tamao Kojima

Inventor： Akihito Hatakeyama ,  Seiichi Nakatani ,  Kouji Kawakita ,  Hiroshi Sogou ,  Tatsuo Ogawa ,  Tamao Kojima

IPC: H05K336

CPC classification number: H05K3/462 ,  H05K1/0366 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0116 ,  H05K2201/0154 ,  H05K2201/0278 ,  H05K2201/0355 ,  H05K2201/10378 ,  H05K2201/2072 ,  H05K2203/0191 ,  H05K2203/1461 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T428/24917 ,  Y10T428/249953 ,  Y10T428/249996

Abstract: A printed circuit board includes an uncured substrate material with closed voids which are disposed with a through-hole. When the through-hole is formed, voids which exist in the substrate material open from inner wall of the through-hole to form a hollow-shaped part. By filling the through-hole and the hollow-shaped part with conductive paste, the adhesion improves by the increased holding effect between the conductive paste and the wall surface of the through-hole.

公开(公告)号：US6166334A

公开(公告)日：2000-12-26

申请号：US287549

申请日：1999-04-06

Applicant: Terry R. Galloway

Inventor： Terry R. Galloway

IPC: B23K3/06 ,  H05K3/00 ,  H05K3/34 ,  H01R12/04 ,  H05K1/11

CPC classification number: B23K3/06 ,  B23K3/0623 ,  B23K2101/40 ,  H01L2924/00013 ,  H05K3/0035 ,  H05K3/3436 ,  H05K3/3473 ,  H05K2201/0116 ,  H05K2201/10674 ,  H05K2203/0191 ,  Y02P70/613 ,  Y10T29/49149 ,  H01L2224/29099

Abstract: Apertures in a tape formed on a substrate allow straight plating of solder bumps to heights above 4 mils. The solder bumps are combined with a lower density material to form an hourglass-shaped structure which allows interconnections to bonding pads of electronic components with pitches less than 9 mils.

Abstract translation: 形成在基板上的带的孔径允许将焊料凸块直线电镀到高于4密耳的高度。 焊料凸块与较低密度的材料组合以形成沙漏形结构，其允许与间距小于9密耳的电子部件的焊盘相互连接。

公开(公告)号：US6052286A

公开(公告)日：2000-04-18

申请号：US57357

申请日：1998-04-08

Applicant: Karl L. Worthen ,  Leon Stiborek

Inventor： Karl L. Worthen ,  Leon Stiborek

IPC: H01R4/04 ,  H01R13/24 ,  H05K3/32 ,  H05K3/46 ,  H05K1/03

CPC classification number: H01R13/2414 ,  H01R4/04 ,  H05K3/323 ,  H05K3/4614 ,  H05K2201/0116 ,  H05K2201/09536 ,  H05K2201/10378 ,  H05K3/4623

Abstract: A polymeric three-layer membrane having metal-filled microscopic pores extending through the complete thickness of the membrane, including a central restraining core layer, and an adhesive layer on each surface of the core layer. The membrane is used to form interconnects between electronic parts.

Abstract translation: 聚合物三层膜，其具有延伸穿过膜的整个厚度的金属填充的微孔，包括中心抑制芯层，以及在芯层的每个表面上的粘合剂层。 膜用于形成电子部件之间的互连。

公开(公告)号：US6034875A

公开(公告)日：2000-03-07

申请号：US98977

申请日：1998-06-17

Applicant: Craig G. Heim ,  Wade Leslie Hooker ,  Ajit Kumar Trivedi

Inventor： Craig G. Heim ,  Wade Leslie Hooker ,  Ajit Kumar Trivedi

IPC: H01L21/60 ,  H01L23/367 ,  H05K3/22 ,  H05K3/34 ,  H05K7/20

CPC classification number: H01L24/81 ,  H01L23/3672 ,  H01L24/75 ,  H05K3/3494 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/75 ,  H01L2224/755 ,  H01L2224/75745 ,  H01L2224/7999 ,  H01L2224/81801 ,  H01L2224/98 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3025 ,  H05K2201/0116 ,  H05K2201/10522 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/0195 ,  H05K2203/0776 ,  H05K2203/081 ,  H05K2203/1121 ,  H05K2203/176 ,  H05K2203/304 ,  H05K3/225 ,  Y10T29/4913 ,  Y10T29/4973 ,  Y10T29/49815 ,  Y10T29/49821 ,  Y10T29/53174

Abstract: A method and apparatus for cooling electrical components on a substrate during a rework process. A block of a porous, thermally conductive material, saturated with a liquid, is positioned on an electrical component to be cooled. During the rework processing of an adjacent electrical component, the liquid in the porous, thermally conductive block vaporizes, thereby maintaining the temperature of the electrical component below its reflow temperature. A second thermally conductive block, in thermal contact with the porous, thermally conductive block, and the substrate on which the electronic component to be cooled is attached, is positioned between the electronic component to be cooled and the electronic component undergoing rework. A supply of liquid is provided to the porous, thermally conductive block to maintain the temperature of the electronic component to be cooled at a predetermined level for a specified period of time.

Abstract translation: 一种用于在返工过程中冷却基板上的电气部件的方法和设备。 用液体饱和的多孔导热材料块被定位在待冷却的电气部件上。 在相邻电气部件的返工处理期间，多孔导热块中的液体蒸发，从而将电气部件的温度保持在其回流温度以下。 与多孔导热块热接触的第二导热块以及待冷却的电子部件所附接的基板位于待冷却的电子部件和正在进行返工的电子部件之间。 向多孔导热块提供液体供应，以将待冷却的电子部件的温度保持在预定水平一段指定的时间。

公开(公告)号：US6033765A

公开(公告)日：2000-03-07

申请号：US102542

申请日：1998-06-23

Applicant: Tsutomu Takahashi ,  Yoshifumi Tsujimoto ,  Hiroaki Kumada ,  Hiroyuki Sato

Inventor： Tsutomu Takahashi ,  Yoshifumi Tsujimoto ,  Hiroaki Kumada ,  Hiroyuki Sato

IPC: B32B15/14 ,  C08J5/04 ,  C08J5/24 ,  C09D5/25 ,  H05K1/03 ,  B23B3/00

CPC classification number: C08J5/24 ,  B32B15/14 ,  C08J5/04 ,  H05K1/0366 ,  H05K2201/0116 ,  H05K2201/0129 ,  H05K2201/0278 ,  H05K2201/0293 ,  H05K2201/068 ,  Y10S428/901 ,  Y10S428/902 ,  Y10S428/91 ,  Y10T428/24917 ,  Y10T428/24993 ,  Y10T428/24994 ,  Y10T428/249944 ,  Y10T428/249953 ,  Y10T428/249955 ,  Y10T428/2907 ,  Y10T428/2938 ,  Y10T428/2969 ,  Y10T428/2971 ,  Y10T428/30 ,  Y10T428/31678 ,  Y10T428/31681 ,  Y10T428/31725 ,  Y10T442/2008 ,  Y10T442/2893 ,  Y10T442/2902

Abstract: The present invention provides a printed circuit substrate comprising a lightweight prepreg and a conductive layer. The prepeg having uniform formation, low linear thermal expansion coefficient and good mechanical strength, comprising a porous para-oriented aromatic polyamide film and a thermoplastic resin and/or a thermosetting resin, the porous para-oriented aromatic polyamide film being impregnated with the thermoplastic resin and/or the thermosetting resin, a process for producing the same, and a printed circuit substrate/board using the same.

Abstract translation: 本发明提供一种印刷电路基板，包括轻质预浸料和导电层。 包含多孔对位芳族聚酰胺薄膜和热塑性树脂和/或热固性树脂的具有均匀形成，低线性热膨胀系数和良好机械强度的预成型体，多孔对位芳族聚酰胺薄膜浸渍有热塑性树脂 和/或热固性树脂，其制备方法和使用其的印刷电路基板/印刷电路板。

公开(公告)号：US5957370A

公开(公告)日：1999-09-28

申请号：US781740

申请日：1997-01-10

Applicant: Terry R. Galloway

Inventor： Terry R. Galloway

IPC: B23K3/06 ,  H05K3/00 ,  H05K3/34 ,  B23K31/02

CPC classification number: B23K3/06 ,  B23K3/0623 ,  H05K3/3436 ,  H05K3/3473 ,  B23K2201/40 ,  H01L2924/00013 ,  H05K2201/0116 ,  H05K2201/10674 ,  H05K2203/0191 ,  H05K3/0035 ,  Y02P70/613 ,  Y10T29/49149

Abstract: Apertures in a tape formed on a substrate allow straight plating of solder bumps to heights above 4 mils. The solder bumps are combined with a lower density material to form an hourglass-shaped structure which allows interconnections to bonding pads of electronic components with pitches less than 9 mils.

公开(公告)号：US5833759A

公开(公告)日：1998-11-10

申请号：US747170

申请日：1996-11-08

Applicant: Randy E. Haslow ,  Donald G. Hutchins ,  Michael R. Leaf

Inventor： Randy E. Haslow ,  Donald G. Hutchins ,  Michael R. Leaf

IPC: H01L21/28 ,  H01L21/48 ,  H01L21/768 ,  H01L23/12 ,  H05K3/00 ,  H05K3/26 ,  H05K3/46 ,  B08B3/12 ,  B44C1/22 ,  H01B13/00

CPC classification number: H01L21/486 ,  H05K3/0032 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K3/0035 ,  H05K3/0055 ,  H05K3/4652

Abstract: The invention relates to a method for cleaning vias in electronic component substrates prior to metallization thereof.

Abstract translation: 本发明涉及一种在金属化之前清洁电子部件基板中的通孔的方法。