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    In situ method of forming a bypass capacitor element internally within a capacitive PCB
    81.
    发明授权
    In situ method of forming a bypass capacitor element internally within a capacitive PCB 失效
    在电容PCB内部形成旁路电容元件的原位方法

    公开(公告)号：US5800575A

    公开(公告)日：1998-09-01

    申请号：US147671

    申请日：1993-11-03

    Applicant: Gregory L. Lucas

    Inventor： Gregory L. Lucas

    IPC: H05K1/03 ,  H05K1/16 ,  H05K3/38 ,  H05K3/46 ,  H01G4/40

    CPC classification number: H05K3/4641 ,  H05K1/0373 ,  H05K1/162 ,  H05K1/0366 ,  H05K2201/015 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K3/385 ,  H05K3/386 ,  H05K3/4611 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/49144

    Abstract: An in situ method for forming a bypass capacitor element internally within a PCB comprising the steps of arranging one or more uncured dielectric sheets with conductive foils on opposite sides thereof and laminating the conductive foils to the dielectric sheet simultaneously as the PCB is formed by a final lamination step, the conductive foils preferably being laminated to another layer of the PCB prior to their arrangement adjacent the dielectric sheet or sheets, the dielectric foils even more preferably being initially laminated to additional dielectric sheets in order to form multiple bypass capacitive elements as a compound subassembly within the PCB. A number of different dielectric materials and resins are disclosed for forming the capacitor element. A dielectric component in the capacitor element preferably includes dielectric material and thermally responsive material, the thermally responsive material either forming a carrier for the dielectric material or formed as two separate sheets on opposite sides of a sheet of the dielectric material.

    Abstract translation: 用于在PCB内部形成旁路电容器元件的原位方法包括以下步骤：在导电箔的相对侧上布置一个或多个未固化的电介质片，并且当导电箔同时由PCB形成时，将导电箔层压到电介质片上 层压步骤，导电箔优选地在邻近电介质片或片之前层压到PCB的另一层上，电介质箔甚至更优选最初层压到附加的电介质片上，以形成多个旁路电容元件作为化合物 PCB内的子组件。 公开了用于形成电容器元件的许多不同介电材料和树脂。 电容器元件中的电介质元件优选地包括电介质材料和热响应材料，该热响应材料形成用于电介质材料的载体或者在电介质材料片的相对侧上形成为两个分开的片。

    Parallel processor structure and package
    87.
    发明授权
    Parallel processor structure and package 失效
    并行处理器结构和封装

    公开(公告)号：US5379193A

    公开(公告)日：1995-01-03

    申请号：US97520

    申请日：1993-07-27

    Applicant: Thomas P. Gall ,  James R. Loomis

    Inventor： Thomas P. Gall ,  James R. Loomis

    IPC: G06F1/18 ,  G06F15/173 ,  G06F15/80 ,  G11C5/00 ,  H01L21/822 ,  H01L23/52 ,  H01L27/04 ,  H05K1/03 ,  H05K3/00 ,  H05K3/46 ,  H05K1/14

    CPC classification number: H05K3/4691 ,  H05K1/0373 ,  H05K2201/015 ,  H05K2201/09109 ,  H05K2201/10159 ,  H05K3/4641

    Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate.

    Abstract translation: 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。

    Parallel processor and method of fabrication
    88.
    发明授权
    Parallel processor and method of fabrication 失效
    并行处理器和制造方法

    公开(公告)号：US5347710A

    公开(公告)日：1994-09-20

    申请号：US098485

    申请日：1993-07-27

    Applicant: Thomas P. Gall ,  Howard L. Heck ,  John S. Kresge

    Inventor： Thomas P. Gall ,  Howard L. Heck ,  John S. Kresge

    IPC: H01L23/52 ,  G06F15/173 ,  G06F15/80 ,  H05K1/00 ,  H05K1/03 ,  H05K3/00 ,  H05K3/46 ,  H05K3/36

    CPC classification number: H05K3/4635 ,  H05K3/462 ,  H05K1/0373 ,  H05K1/0393 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/09109 ,  H05K2201/09536 ,  H05K2201/10159 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4641 ,  Y10T29/49126 ,  Y10T29/49155

    Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication. The planar circuitization, as data lines, address lines, and control lines of a logic chip or a memory chip are on the individual printed circuit boards and cards, which are connected through the circuitized flex, and communicate with other layers of flex through Z-axis circuitization (vias and through holes) in the laminate.

    Abstract translation: 公开了一种并行处理器封装结构和用于制造该结构的方法。 单独的逻辑和存储器元件在印刷电路卡上。 这些印刷电路板和卡依次安装在或连接到从电路化的柔性基板的层叠体向外延伸的电路化柔性基板上。 通过在层压板中实现的开关结构来提供互通。 印刷电路卡安装在或连接到多个电路化的柔性基板上，在电路化柔性电路的每一端具有一个印刷电路卡。 电路化的柔性基板通过中央层压体部分连接分开的印刷电路板和卡。 该层压部分为处理器间，存储器间，处理器间/存储器元件以及处理器到存储器总线互连和通信提供XY平面和Z轴互连。 作为逻辑芯片或存储器芯片的数据线，地址线和控制线的平面电路在通过电路化的柔性连接的各个印刷电路板和卡上，并且通过Z轴与其它柔性层通信， 轴向电路（通孔和通孔）。

    Method of manufacturing a multilayer circuit board
    90.
    发明授权
    Method of manufacturing a multilayer circuit board 失效
    制造多层电路板的方法

    公开(公告)号：US5274912A

    公开(公告)日：1994-01-04

    申请号：US939105

    申请日：1992-09-01

    Applicant: John A. Olenick ,  Robert C. Daigle

    Inventor： John A. Olenick ,  Robert C. Daigle

    IPC: H05K1/03 ,  H05K3/20 ,  H05K3/32 ,  H05K3/42 ,  H05K3/46 ,  H05K3/36

    CPC classification number: H05K3/4632 ,  H05K3/4617 ,  H05K3/4629 ,  H05K1/0306 ,  H05K2201/0129 ,  H05K2201/015 ,  H05K2201/09563 ,  H05K2203/061 ,  H05K3/205 ,  H05K3/328 ,  H05K3/423 ,  H05K3/4688 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: Methods of fabricating multilayer circuits are presented. In accordance with the present invention, a plurality of circuit layers comprised of a dielectric substrate having a circuit formed thereon are stacked, one on top of the other. The dielectric substrate is composed of a polymeric material capable of undergoing fusion bonding such as a fluoropolymeric based substrate. The circuits each include a layer of a noble metal at, at least, selected exposed locations. Once stacked the circuits are subjected to lamination under heat and pressure to simultaneously fuse all of the substrate and diffuse conductive layers together to form an integral multilayer circuit having solid conductive interconnects.

    Abstract translation: 介绍了制作多层电路的方法。 根据本发明，由其上形成有电路的电介质基板组成的多个电路层彼此堆叠。 电介质基板由能够进行熔融粘合的聚合材料构成，例如基于氟聚合物的基材。 这些电路各自包括至少在选定的暴露位置处的贵金属层。 一旦堆叠，电路在加热和压力下进行层压，以将所有基板和扩散导电层同时融合在一起，形成具有固体导电互连的整体多层电路。

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