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    Process of making a metal core printed circuit board
    81.
    发明授权
    Process of making a metal core printed circuit board 失效
    制造金属核心印刷电路板的工艺

    公开(公告)号：US3745095A

    公开(公告)日：1973-07-10

    申请号：US3745095D

    申请日：1971-01-26

    Applicant: INT ELECTRONIC RES CORP

    Inventor： CHADWICK D ,  MUELLER W ,  APODACA R

    IPC: H05K1/05 ,  H05K3/06 ,  H05K3/10 ,  H05K3/18 ,  H05K3/24 ,  H05K3/38 ,  H05K3/42 ,  H05K3/44 ,  C23B5/48

    CPC classification number: H05K3/24 ,  H05K1/056 ,  H05K3/062 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/0209 ,  H05K2201/0344 ,  H05K2203/025 ,  H05K2203/1105

    Abstract: The invention is a method for making a metal core printed circuit board which includes applying multiple layers of synthetic plastic resin material to a sheet of metal, then treating the surface of the plastic material in such a way as to provide an acceptable bond, followed by applying sundry layers of different metals, first to the plastic surface and then one upon another followed by the imposition of a circuit pattern, the removal of materials from areas intermediate the circuit pattern, and the application of an appropriate overlay of unlike metal to the circuit pattern, thereby to provide a finished circuit board.

    Abstract translation: 本发明是一种用于制造金属芯印刷电路板的方法，其包括将多层合成塑料树脂材料施加到金属片上，然后以提供可接受的粘合剂的方式处理塑料材料的表面，接着是 应用各种不同金属层，首先到塑料表面，然后一个接一个地接着施加电路图案，从电路图案之间的区域去除材料，以及将不同于金属的合适覆盖层施加到电路 图案，从而提供成品电路板。

    WIRING BOARD
    86.
    发明公开
    WIRING BOARD 审中-公开

    公开(公告)号：US20240292533A1

    公开(公告)日：2024-08-29

    申请号：US18572428

    申请日：2022-06-13

    Applicant: KYOCERA Corporation

    Inventor： Hidetoshi YUGAWA

    IPC: H05K1/09 ,  H05K1/02 ,  H05K3/42

    CPC classification number: H05K1/09 ,  H05K1/0271 ,  H05K3/427 ,  H05K2201/0344 ,  H05K2201/0352 ,  H05K2203/072 ,  H05K2203/0726

    Abstract: A wiring board according to the present disclosure includes an insulation layer, and a wiring conductor positioned on the insulation layer. The wiring conductor includes a phosphorus-containing electroless copper-plating layer positioned on the insulation layer, a nickel-containing electroless copper-plating layer positioned on the phosphorus-containing electroless copper-plating layer, and an electrolytic copper-plating layer positioned on the nickel-containing electroless copper-plating layer.

    Circuit board and manufacturing method thereof
    87.
    发明授权
    Circuit board and manufacturing method thereof 有权
    电路板及其制造方法

    公开(公告)号：US09591753B2

    公开(公告)日：2017-03-07

    申请号：US14849614

    申请日：2015-09-10

    Applicant: Subtron Technology Co., Ltd.

    Inventor： Chin-Sheng Wang ,  Ching-Sheng Chen ,  Mei-Chin Chang ,  Ching-Ta Chen

    IPC: H05K1/09 ,  H05K1/11 ,  H05K3/18

    CPC classification number: H05K1/09 ,  H05K1/111 ,  H05K3/181 ,  H05K3/188 ,  H05K3/244 ,  H05K2201/0338 ,  H05K2201/0344 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2203/072

    Abstract: A circuit board includes a substrate, a patterned copper layer, a phosphorous-containing electroless plating palladium layer, an electroless plating palladium layer and an immersion plating gold layer. The patterned copper layer is disposed on the substrate. The phosphorous-containing electroless plating palladium layer is disposed on the patterned copper layer, wherein in the phosphorous-containing electroless plating palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in a range from 94% to 96%. The electroless plating palladium layer is disposed on the phosphorous-containing electroless plating palladium layer, wherein in the electroless plating palladium layer, a weight percentage of palladium is 99% or more. The immersion plating gold layer is disposed on the electroless plating palladium layer.

    Abstract translation: 电路板包括基板，图案化铜层，含磷化学镀钯层，无电镀钯层和浸镀金层。 图案化铜层设置在基板上。 含磷化学镀钯层设置在图案化的铜层上，其中，在含磷化学镀钯层中，磷的重量百分比为4〜6％，钯的重量百分比为 在94％至96％的范围内。 无电镀钯层配置在含磷化学镀钯层上，其中，在化学镀钯层中，钯的重量百分比为99％以上。 浸镀金层设置在化学镀钯层上。

    PACKAGE SUBSTRATE COMPRISING SURFACE INTERCONNECT AND CAVITY COMPRISING ELECTROLESS FILL
    89.
    发明申请
    PACKAGE SUBSTRATE COMPRISING SURFACE INTERCONNECT AND CAVITY COMPRISING ELECTROLESS FILL 有权
    包含表面互连和包含电镀膜的孔的包装基底

    公开(公告)号：US20150296616A1

    公开(公告)日：2015-10-15

    申请号：US14251486

    申请日：2014-04-11

    Applicant: QUALCOMM Incorporated

    Inventor： Houssam Wafic Jomaa ,  Omar James Bchir ,  Chin-Kwan Kim

    IPC: H05K1/11 ,  H05K3/42 ,  H05K1/02

    CPC classification number: H05K1/112 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K3/422 ,  H05K3/425 ,  H05K3/429 ,  H05K2201/0344 ,  H05K2201/09036 ,  H05K2201/10378

    Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a first electroless metal layer. The first dielectric layer includes a first surface and a second surface. The first interconnect is on the first surface of the substrate layer. The first cavity traverses the first surface of the first dielectric layer. The first electroless metal layer is formed at least partially in the first cavity. The first electroless metal layer defines a second interconnect embedded in the first dielectric layer. In some implementations, the substrate further includes a core layer. The core layer includes a first surface and a second surface. The first surface of the core layer is coupled to the second surface of the first dielectric layer. In some implementations, the substrate further includes a second dielectric layer.

    Abstract translation: 一些新颖特征涉及包括第一介电层，第一互连，第一空腔和第一无电金属层的基板。 第一电介质层包括第一表面和第二表面。 第一互连在衬底层的第一表面上。 第一空腔穿过第一介电层的第一表面。 第一无电金属层至少部分地形成在第一腔中。 第一无电金属层限定嵌入在第一介电层中的第二互连。 在一些实施方案中，衬底还包括芯层。 芯层包括第一表面和第二表面。 芯层的第一表面耦合到第一介电层的第二表面。 在一些实施方案中，衬底还包括第二介电层。

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