公开(公告)号：US08354688B2

公开(公告)日：2013-01-15

申请号：US13337054

申请日：2011-12-24

Applicant: Charles W. C. Lin ,  Chia-Chung Wang

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L33/00

CPC classification number: H05K1/021 ,  H01L21/486 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/4084 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/10106 ,  H05K2203/049 ,  H05K2203/063 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Abstract translation: 半导体芯片组件包括半导体器件，散热器，导电迹线和双重粘合剂。 散热器包括凸块，底座和凸缘。 导电迹线包括焊盘和端子。 半导体器件安装在凸块中的凸起中的凸起中，电连接到导电迹线并且热连接到散热器。 凸块延伸到第一粘合剂中的开口中并且与第二粘合剂中的开口对准并与之隔开。 底座和凸缘从凸块横向延伸。 第一粘合剂被夹在基部和凸缘之间，第二粘合剂夹在导电迹线和凸缘之间，并且凸缘夹在粘合剂之间。 导电迹线位于腔体外部，并在焊盘和端子之间提供信号路由。

公开(公告)号：US08354283B2

公开(公告)日：2013-01-15

申请号：US13337164

申请日：2011-12-26

Applicant: Charles W. C. Lin ,  Chia-Chung Wang

Inventor： Charles W. C. Lin ,  Chia-Chung Wang

IPC: H01L21/00

CPC classification number: H05K1/021 ,  H01L21/486 ,  H01L23/3677 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L33/483 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01087 ,  H01L2924/12041 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K3/4084 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/10106 ,  H05K2203/049 ,  H05K2203/063 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of making a semiconductor chip assembly includes providing a bump and a ledge, mounting a first adhesive on the ledge including inserting the bump into an opening in the first adhesive, mounting a conductive layer on the first adhesive including aligning the bump with an aperture in the conductive layer, then flowing the first adhesive between the bump and the conductive layer, solidifying the first adhesive, then providing a heat spreader that includes the bump, a base and the ledge, then mounting a second adhesive on the ledge, mounting a conductive trace that includes a pad and a terminal on the second adhesive, then mounting a semiconductor device on the bump in a cavity in the bump, electrically connecting the semiconductor device to the conductive trace and thermally connecting the semiconductor device to the heat spreader.

Abstract translation: 制造半导体芯片组件的方法包括提供凸块和凸缘，将第一粘合剂安装在凸缘上，包括将凸块插入第一粘合剂中的开口中，将导电层安装在第一粘合剂上，包括使凸块与孔 在导电层中，然后使第一粘合剂在凸起和导电层之间流动，固化第一粘合剂，然后提供包括凸块，底座和凸缘的散热器，然后将第二粘合剂安装在凸缘上， 导电迹线，其包括第二粘合剂上的焊盘和端子，然后将凸块中的半导体器件安装在凸块中的空腔中，将半导体器件电连接到导电迹线并将半导体器件热连接到散热器。

公开(公告)号：US20120318568A1

公开(公告)日：2012-12-20

申请号：US13521352

申请日：2011-01-07

Applicant: Keisuke Yamanishi ,  Ryo Fukuchi ,  Kengo Kaminaga

Inventor： Keisuke Yamanishi ,  Ryo Fukuchi ,  Kengo Kaminaga

IPC: H05K1/02 ,  B32B15/08 ,  H05K3/06

CPC classification number: H05K1/09 ,  B32B15/04 ,  B32B15/20 ,  C23C18/1651 ,  C23C18/1653 ,  C25D5/10 ,  C25D7/0614 ,  H05K3/06 ,  H05K2201/0154 ,  H05K2201/0338 ,  H05K2201/0355 ,  Y10T428/12542 ,  Y10T428/12569

Abstract: Provided is an electronic circuit as a laminated body configured from a layer (A) which is made of a copper or copper alloy foil formed on one surface or both surfaces of a resin substrate, a copper or copper alloy plated layer (B) formed on a part or whole surface of the (A) layer, a plated layer (C) formed on a part or whole surface of the (B) layer and having a slower etching rate than that of copper relative to a copper etching solution, and a copper or copper alloy plated layer (D) formed on the layer (C) and which has a thickness of 0.05 μm or more and less than 1 μm, and which is made of a copper circuit formed by etching and removing a part of the laminated portion of the (A) layer, the (B) layer, the (C) layer and the (D) layer up to the resin substrate surface. It is thereby possible to form a circuit having a uniform circuit width, improve the etching properties in pattern etching, and prevent the occurrence of short-circuits and defects in the circuit width.

Abstract translation: 本发明提供一种作为层叠体的电子电路，其由在由树脂基板，铜或铜合金镀层（B）的一个面或两面上形成的铜或铜合金箔构成的层（A）构成， （A）层的一部分或整个表面，形成在（B）层的一部分或整个表面上并且具有比铜蚀刻溶液的蚀刻速率慢的蚀刻速率的镀层（C），以及 铜或铜合金镀层（D），其形成在层（C）上，厚度为0.05μm以上且小于1μm，由铜电路构成，该铜电路通过蚀刻除去部分层叠体 部分（A）层，（B）层，（C）层和（D）层直到树脂基板表面。 从而可以形成具有均匀电路宽度的电路，改善图案蚀刻中的蚀刻性能，并且防止电路宽度的短路和缺陷的发生。

公开(公告)号：US20120227258A1

公开(公告)日：2012-09-13

申请号：US13478026

申请日：2012-05-22

Applicant: Christopher A. Hunrath

Inventor： Christopher A. Hunrath

IPC: H05K3/30 ,  B32B37/00

CPC classification number: H05K1/09 ,  H05K1/0271 ,  H05K3/025 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4682 ,  H05K3/4688 ,  H05K2201/0154 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2203/0152 ,  H05K2203/1536 ,  Y10T29/4913 ,  Y10T156/10 ,  Y10T428/31678 ,  Y10T428/31721

Abstract: One or more embodiments contained herein disclose rigid printed circuit boards (PCBs) and methods for manufacturing the same comprising strain resistant layers configured to, among others, minimize defects from occurring in cap layers of the PCBs.

Abstract translation: 本文包含的一个或多个实施方案公开了刚性印刷电路板（PCB）及其制造方法，其包括抗应变层，其特征在于，最小化PCB中盖层中发生的缺陷。

公开(公告)号：US08257820B2

公开(公告)日：2012-09-04

申请号：US12370806

申请日：2009-02-13

Applicant: Sankar Paul ,  Dirk M. Baars

Inventor： Sankar Paul ,  Dirk M. Baars

IPC: B32B7/12 ,  B32B27/32

CPC classification number: H05K1/0373 ,  B32B7/12 ,  B32B15/06 ,  B32B15/08 ,  B32B15/085 ,  B32B15/20 ,  B32B27/285 ,  B32B27/32 ,  B32B2255/06 ,  B32B2255/10 ,  B32B2255/26 ,  B32B2262/0276 ,  B32B2264/0278 ,  B32B2307/204 ,  B32B2307/302 ,  B32B2307/3065 ,  B32B2307/50 ,  B32B2307/54 ,  B32B2307/714 ,  B32B2307/7265 ,  B32B2307/734 ,  B32B2457/00 ,  C08K3/22 ,  C08L15/00 ,  C08L19/006 ,  C08L71/12 ,  C08L2666/14 ,  C09D5/24 ,  C09D7/61 ,  C09J107/00 ,  C12Q1/6886 ,  C12Q2600/154 ,  C12Q2600/156 ,  H05K1/032 ,  H05K3/386 ,  H05K3/4626 ,  H05K2201/012 ,  H05K2201/0133 ,  H05K2201/0158 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0355 ,  H05K2203/122 ,  Y10T156/10 ,  Y10T428/24802 ,  Y10T428/2804 ,  Y10T428/31826 ,  Y10T428/31833 ,  Y10T428/31855 ,  Y10T428/31909 ,  Y10T428/31924 ,  Y10T428/31931 ,  Y10T428/31938 ,  C08L2666/08

Abstract: A circuit subassembly, comprising: a conductive layer, a dielectric layer formed from a thermosetting composition, wherein the thermosetting composition comprises, based on the total weight of the thermosetting composition a polybutadiene or polyisoprene resin, about 30 to about 70 percent by weight of a magnesium hydroxide having less than about 1000 ppm of ionic contaminants, and about 5 to about 15 percent by weight of a nitrogen-containing compound, wherein the nitrogen-containing compound comprises at least about 15 weight percent of nitrogen; and an adhesive layer disposed between and in intimate contact with the conductive layer and the dielectric layer, wherein the adhesive comprises a poly(arylene ether), wherein the circuit subassembly has a UL-94 rating of at least V-1.

Abstract translation: 一种电路子组件，包括：导电层，由热固性组合物形成的电介质层，其中所述热固性组合物基于所述热固性组合物的总重量包含聚丁二烯或聚异戊二烯树脂，约30至约70重量％ 具有小于约1000ppm的离子污染物的氢氧化镁和约5至约15重量％的含氮化合物，其中所述含氮化合物包含至少约15重量％的氮; 以及设置在所述导电层和所述电介质层之间并且与所述电介质层紧密接触的粘合剂层，其中所述粘合剂包括聚（亚芳基醚），其中所述电路子组件具有至少V-1的UL-94等级。

公开(公告)号：US20120218721A1

公开(公告)日：2012-08-30

申请号：US13467077

申请日：2012-05-09

Applicant: Shigeo NISHIMURA

Inventor： Shigeo NISHIMURA

IPC: H05K7/00 ,  H05K3/30

CPC classification number: H05K1/188 ,  H05K3/245 ,  H05K2201/0355 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913

Abstract: A method of manufacturing a component built-in module includes a step of preparing a sheet metal; a step of providing a conductive thick-film pad over one main surface of the sheet metal by applying and curing a conductive paste; a step of providing a joining material over the conductive thick-film pad; a step of mounting a chip component onto the conductive thick-film pad with the joining material interposed therebetween; a step of providing a resin layer over the one main surface so as to cover the chip component; and a step of forming a surface electrode by patterning the sheet metal.

Abstract translation: 制造组件内置模块的方法包括制备金属板的步骤; 通过施加和固化导电浆料在金属片的一个主表面上提供导电厚膜垫的步骤; 在导电厚膜垫上提供接合材料的步骤; 将芯片部件安装在导电性厚膜焊盘上，其间插入有接合材料的步骤; 在一个主表面上设置树脂层以覆盖芯片部件的步骤; 以及通过图案化金属板来形成表面电极的步骤。

公开(公告)号：US08252166B2

公开(公告)日：2012-08-28

申请号：US13243187

申请日：2011-09-23

Applicant: Yousuke Kobayashi ,  Atsushi Miki ,  Keisuke Yamanishi

Inventor： Yousuke Kobayashi ,  Atsushi Miki ,  Keisuke Yamanishi

IPC: C25D3/38 ,  C25D5/00

CPC classification number: H05K3/384 ,  C22C9/00 ,  C22C9/02 ,  C22C9/04 ,  C22C9/06 ,  C25D3/38 ,  C25D5/10 ,  C25D7/0614 ,  C25D7/0692 ,  H05K2201/0355 ,  H05K2203/0307 ,  H05K2203/0723 ,  Y10T428/12014 ,  Y10T428/12063 ,  Y10T428/12181 ,  Y10T428/12431 ,  Y10T428/12438 ,  Y10T428/12903 ,  Y10T428/1291 ,  Y10T428/12993

Abstract: A rolled copper or copper alloy foil having a roughened surface formed of fine copper particles is obtained by subjecting a rolled foil to roughening plating with a plating bath containing copper sulfate (Cu equivalent of 1 to 50 g/L), 1 to 150 g/L of sulfuric acid, and one or more additives selected among sodium octyl sulfate, sodium decyl sulfate, and sodium dodecyl sulfate under the conditions of temperature of 20 to 50° C. and current density of 10 to 100 A/dm2. The foil has reduced craters, which are defects unique to rolled foils having a roughened surface, has high strength, adhesive strength with the resin layer, acid resistance and anti-tin plating solution properties, high peel strength, favorable etching properties and gloss level, and is suitable for producing a flexible printed wiring board capable of bearing a fine wiring pattern. A method of roughening the rolled foil is also provided.

Abstract translation: 通过使用含有硫酸铜（Cu当量1〜50g / L），1〜150g / L的电镀液对轧制箔进行粗糙化处理，得到具有由细铜颗粒形成的粗糙面的轧制铜或铜合金箔， L的硫酸，以及一种或多种选自辛基硫酸钠，癸基硫酸钠和十二烷基硫酸钠的添加剂，其温度为20〜50℃，电流密度为10〜100A / dm 2。 箔具有减少的凹坑，这是具有粗糙表面的轧制箔特有的缺陷，具有高强度，与树脂层的粘合强度，耐酸性和抗锡电镀溶液性能，高剥离强度，良好的蚀刻性能和光泽度， 并且适合于制造能够承受精细布线图案的柔性印刷线路板。 还提供了粗糙化轧制箔的方法。

公开(公告)号：US20120205146A1

公开(公告)日：2012-08-16

申请号：US13390403

申请日：2010-08-11

Applicant: Ryoichi Oguro ,  Kazuhiro Hoshino

Inventor： Ryoichi Oguro ,  Kazuhiro Hoshino

IPC: H05K1/09 ,  C25D5/10 ,  B32B15/00 ,  B32B37/10 ,  B32B15/04

CPC classification number: H05K3/384 ,  B32B15/08 ,  B32B15/20 ,  C23C18/122 ,  C25D1/04 ,  C25D3/32 ,  C25D3/38 ,  C25D5/10 ,  C25D5/16 ,  C25D5/48 ,  C25D7/0614 ,  C25D11/38 ,  H05K1/0242 ,  H05K2201/0355 ,  H05K2203/0307 ,  H05K2203/0723 ,  Y10T428/12535 ,  Y10T428/12549 ,  Y10T428/12792

Abstract: Disclosed is a copper foil which has excellent high frequency characteristics and heat resistance, while achieving high heat-resistant adhesion to a resin substrate at the same time. Specifically disclosed is a heat-resistant copper foil which has a configuration wherein a first roughened surface layer which has been treated by a first roughening treatment by copper metal, a second roughened surface layer which has been treated by a second roughening treatment by copper metal, and a third treated surface layer which has been treated by a third treatment process by zinc metal are sequentially provided on one surface of an untreated copper foil. Also specifically disclosed are: a circuit board which is obtained by laminating the heat-resistant copper foil on a flexible resin substrate or a rigid resin substrate; and a method for producing a copper-clad laminate wherein the heat-resistant copper foil and a heat-resistant resin substrate are thermally pressure-bonded and the roughened copper metal and the third treated surface layer of the zinc metal are alloyed.

Abstract translation: 公开了一种具有优异的高频特性和耐热性的铜箔，同时对树脂基板实现高耐热粘合性。 具体公开了一种耐热铜箔，其具有通过铜金属的第一粗糙化处理进行了处理的第一粗糙化表面层，通过铜金属进行第二粗糙化处理的第二粗糙化表面层， 并且在未处理的铜箔的一个表面上依次设置通过第三处理工艺用锌金属处理的第三处理表面层。 还具体公开的是：通过将耐热铜箔层压在柔性树脂基板或刚性树脂基板上而获得的电路板; 以及一种制造覆铜层压板的方法，其中耐热铜箔和耐热树脂基板被热压粘合，并且将粗糙的铜金属和第三被处理的锌金属表面层合金化。

公开(公告)号：US08237255B2

公开(公告)日：2012-08-07

申请号：US12633433

申请日：2009-12-08

Applicant: Sang-Hyun Kim ,  Shi-Yun Cho ,  Young-Min Lee ,  Kyu-Sub Kwak ,  Youn-Ho Choi

Inventor： Sang-Hyun Kim ,  Shi-Yun Cho ,  Young-Min Lee ,  Kyu-Sub Kwak ,  Youn-Ho Choi

IPC: H01L23/48

CPC classification number: H05K1/188 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/82039 ,  H01L2224/92244 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/10674 ,  H05K2203/0554

Abstract: A Printed Circuit Board (PCB) is provided in which at least one built-in Integrated Circuit (IC) package has a plurality of conductive bumps on an IC. The plurality of conductive bumps are for external electrical connection. The IC package is accommodated within a core layer of a multi-layer PCB by a connection member on the IC. The connection member is formed between the conductive bumps and the core layer with contact holes in contact with the conductive bumps. The conductive bumps are electrically connected through conductor layers formed in the contact holes.

Abstract translation: 提供了印刷电路板（PCB），其中至少一个内置集成电路（IC）封装在IC上具有多个导电凸块。 多个导电凸块用于外部电连接。 IC封装通过IC上的连接构件容纳在多层PCB的芯层内。 连接构件形成在导电凸块和芯层之间，其中接触孔与导电凸块接触。 导电凸块通过形成在接触孔中的导体层电连接。

公开(公告)号：US20120189826A1

公开(公告)日：2012-07-26

申请号：US13498764

申请日：2010-09-28

Applicant: Katsura Hayashi

Inventor： Katsura Hayashi

IPC: B32B3/00 ,  B32B9/04 ,  B32B18/00 ,  B32B7/02

CPC classification number: H05K3/4673 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/16225 ,  H05K3/4602 ,  H05K3/4655 ,  H05K2201/0175 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2203/1152 ,  Y10T428/24802 ,  Y10T428/24942

Abstract: A structure for which the electrical reliability is improved is provided. A structure in accordance with one embodiment includes an inorganic insulating layer including amorphous silicon oxide and having an elastic modulus which is 45 GPa or less. A method for manufacturing a structure in accordance with one embodiment includes applying an inorganic insulating sol including inorganic insulating particles composed of amorphous silicon oxide, and forming an inorganic insulating layer including amorphous silicon oxide and having an elastic modulus which is 45 GPa or less by heating the inorganic insulating particles at a temperature lower than a crystallization onset temperature of silicon oxide to each other.

Abstract translation: 提供了改善电可靠性的结构。 根据一个实施方案的结构包括无定形氧化硅的无机绝缘层，其弹性模量为45GPa以下。 根据一个实施方案的结构的制造方法包括：施加包含由无定形氧化硅构成的无机绝缘粒子的无机绝缘溶胶，通过加热形成包含非晶氧化硅的无机绝缘层，其弹性模量为45GPa以下 所述无机绝缘粒子的温度低于氧化硅的结晶化开始温度。