公开(公告)号：US5824454A

公开(公告)日：1998-10-20

申请号：US827335

申请日：1997-03-26

Applicant: Gijsbertus A.C.M. Spierings ,  Willem L.C.M. Heijboer ,  Leo O. Remeeus

Inventor： Gijsbertus A.C.M. Spierings ,  Willem L.C.M. Heijboer ,  Leo O. Remeeus

IPC: G03F7/40 ,  C23F1/00 ,  C23F1/02 ,  C25D13/06 ,  G03F1/08 ,  G03F7/00 ,  G03F7/11 ,  G03F7/16 ,  G03F7/30 ,  H01J9/14 ,  H01J17/49 ,  H01J31/12 ,  H01L21/306 ,  H05K1/03 ,  H05K1/09 ,  H05K3/00 ,  H05K3/06 ,  H05K3/38 ,  G03F7/26

CPC classification number: H01J9/148 ,  G03F7/00 ,  G03F7/0007 ,  G03F7/0015 ,  G03F7/11 ,  H01J9/14 ,  H01J9/146 ,  H05K1/09 ,  H05K3/0094 ,  G03F7/164 ,  H01J2209/012 ,  H01J2329/00 ,  H05K1/0306 ,  H05K2201/09581 ,  H05K2203/135 ,  H05K3/064 ,  H05K3/388

Abstract: A method of metallizing an electrically insulating plate, for example, of glass having a large number of holes. Said relatively small holes are internally provided with a metal layer and the plate is provided with metal tracks. The metal used is mainly aluminum. The aluminum is coated with a thin protective layer of chromium, cobalt, nickel, zirconium or titanium. Said protective layer makes it possible to use a photosensitive, cataphoretic lacquer to mask the metal layer in patterning and etching thereof. The method can very suitably be used for the manufacture of selection plates for thin electron displays.

Abstract translation: 对具有大量孔的玻璃的电绝缘板进行金属化的方法。 所述相对小的孔内部设置有金属层，并且板上设有金属轨道。 所使用的金属主要是铝。 铝被镀有铬，钴，镍，锆或钛的薄保护层。 所述保护层使得可以在其图案化和蚀刻中使用感光性气雾剂来掩蔽金属层。 该方法可以非常适合用于制造薄电子显示器的选择板。

公开(公告)号：US5657537A

公开(公告)日：1997-08-19

申请号：US453109

申请日：1995-05-30

Applicant: Richard Joseph Saia ,  Bernard Gorowitz ,  Kevin Matthew Durocher

Inventor： Richard Joseph Saia ,  Bernard Gorowitz ,  Kevin Matthew Durocher

IPC: H01L21/98 ,  H01L23/538 ,  H01L25/065 ,  H05K1/03 ,  H05K1/14 ,  H05K3/40 ,  H05K3/46 ,  H05K3/36

CPC classification number: H01L25/50 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H05K1/144 ,  H05K3/403 ,  H01L2224/24225 ,  H01L2224/24227 ,  H01L2224/2919 ,  H01L2224/8384 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/0306 ,  H05K2201/09581 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4685 ,  Y10T29/49126

Abstract: A method for fabricating a stack of circuit modules includes providing a plurality of substrates having module interconnection layers. Each of the substrates has a circuit chip with chip pads positioned therein and an electrically conductive feed-through line extending from a first surface of the substrate to a second surface of the substrate with the first surface being perpendicular to the second surface. Each of the module interconnection layers is situated over a respective first surface of each of the substrates and includes a module dielectric layer having module vias therein and a module pattern of electrical conductors extending through the module vias to couple the selected chip pads to the feed-through line. The plurality of substrates are stacked. A side interconnection layer is applied over a side surface including the second surfaces of the substrates. The side interconnection layer includes a side dielectric layer having side vias therein aligned with predetermined ones of the feed-through lines and a side pattern of electrical conductors extending through the side vias.

Abstract translation: 一种用于制造电路模块堆叠的方法包括提供具有模块互连层的多个基板。 每个基板具有其中设置有芯片焊盘的电路芯片，以及导电的馈通线，其从基板的第一表面延伸到基板的第二表面，其中第一表面垂直于第二表面。 每个模块互连层位于每个基板的相应的第一表面上，并且包括其中具有模块通孔的模块介电层和延伸穿过模块通孔的电导体的模块图案，以将所选择的芯片焊盘耦合到馈送 - 通过线。 堆叠多个基板。 侧面互连层被施加在包括基板的第二表面的侧表面上。 侧面互连层包括侧面介电层，其侧面通孔与预定的馈通线对准，并且电导体的侧面图案延伸穿过侧面通孔。

公开(公告)号：US5316787A

公开(公告)日：1994-05-31

申请号：US978309

申请日：1992-11-17

Applicant: Richard F. Frankeny ,  Ronald L. Imken

Inventor： Richard F. Frankeny ,  Ronald L. Imken

IPC: H01L21/60 ,  H01L21/66 ,  H01L23/14 ,  H01L23/373 ,  H01L23/498 ,  H05K1/00 ,  H05K3/42 ,  H05K3/44 ,  C23C26/00

CPC classification number: H05K3/429 ,  H01L23/142 ,  H01L23/3735 ,  H01L23/4985 ,  H05K3/445 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01078 ,  H05K1/0393 ,  H05K2201/0154 ,  H05K2201/068 ,  H05K2201/09581 ,  H05K2201/09718 ,  H05K2201/09881 ,  H05K2203/0323 ,  H05K2203/1438 ,  Y10T29/41

Abstract: A method and system for manufacturing electrically isolated vias in a flexible substrate composed of a metal core laminated by layers of an organic material. The method includes the steps of etching via holes, hydrolyzing the inner organic surfaces of the via holes and baking a polyimide solution coated in the via holes.

Abstract translation: 一种用于制造由通过有机材料层层压的金属芯构成的柔性基板中的电隔离通孔的方法和系统。 该方法包括蚀刻通孔，水解通孔的内部有机表面并烘烤涂覆在通孔中的聚酰亚胺溶液的步骤。

公开(公告)号：US5277725A

公开(公告)日：1994-01-11

申请号：US881448

申请日：1992-05-11

Applicant: John Acocella ,  Peter A. Agostino ,  Arnold I. Baise ,  Richard A. Bates ,  Ray M. Bryant ,  Jon A. Casey ,  David R. Clarke ,  George Czornyj ,  Allen J. Dam ,  Lawrence D. David ,  Renuka S. Divakaruni ,  Werner E. Dunkel ,  Ajay P. Giri ,  Liang-Choo Hsia ,  James N. Humenik ,  Steven M. Kandetzke ,  Daniel P. Kirby ,  John U. Knickerbocker ,  Sarah H. Knickerbocker ,  Anthony Mastreani ,  Amy T. Matts ,  Robert W. Nufer ,  Charles H. Perry ,  Srinivasa S. N. Reddy ,  Salvatore J. Scilla ,  Mark A. Takacs ,  Lovell B. Wiggins

Inventor： John Acocella ,  Peter A. Agostino ,  Arnold I. Baise ,  Richard A. Bates ,  Ray M. Bryant ,  Jon A. Casey ,  David R. Clarke ,  George Czornyj ,  Allen J. Dam ,  Lawrence D. David ,  Renuka S. Divakaruni ,  Werner E. Dunkel ,  Ajay P. Giri ,  Liang-Choo Hsia ,  James N. Humenik ,  Steven M. Kandetzke ,  Daniel P. Kirby ,  John U. Knickerbocker ,  Sarah H. Knickerbocker ,  Anthony Mastreani ,  Amy T. Matts ,  Robert W. Nufer ,  Charles H. Perry ,  Srinivasa S. N. Reddy ,  Salvatore J. Scilla ,  Mark A. Takacs ,  Lovell B. Wiggins

IPC: H05K1/03 ,  C04B41/48 ,  C04B41/49 ,  H01L21/48 ,  H01L23/08 ,  H01L23/538 ,  H05K3/40 ,  C04B37/00 ,  B05D5/12

CPC classification number: H01L21/4857 ,  C04B41/488 ,  C04B41/4961 ,  H01L23/5383 ,  H05K3/4061 ,  C04B2111/00672 ,  C04B2111/00844 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H05K1/0306 ,  H05K2201/09581 ,  H05K2203/1147 ,  H05K2203/308

Abstract: The cracking experienced during thermal cycling of metal:dielectric semiconductor packages results from a mismatch in thermal co-efficients of expansion. The non-hermeticity associated with such cracking can be addressed by backfilling the permeable cracks with a flexible material. Uniform gaps between the metal and dielectric materials can similarly be filled with flexible materials to provide stress relief, bulk compressibility and strength to the package. Furthermore, a permeable, skeletal dielectric can be fabricated as a fired, multilayer structure having sintered metallurgy and subsequently infused with a flexible, temperature-stable material to provide hermeticity and strength.

Abstract translation: 在金属的热循环过程中经历的裂纹：电介质半导体封装是由热膨胀系数不匹配引起的。 与这种开裂相关的非气密性可以通过用柔性材料回填可渗透裂缝来解决。 金属和电介质材料之间的均匀间隙可以类似地填充柔性材料，以提供应力消除，体积可压缩性和包装的强度。 此外，可渗透的骨架电介质可以被制造为具有烧结冶金的烧结多层结构，并随后注入柔性的温度稳定的材料以提供气密性和强度。

公开(公告)号：US5275694A

公开(公告)日：1994-01-04

申请号：US855258

申请日：1992-03-23

Applicant: Hideaki Yamaguchi ,  Hideyuki Kawai ,  Daikichi Tachibana ,  Kenichi Yamaguchi

Inventor： Hideaki Yamaguchi ,  Hideyuki Kawai ,  Daikichi Tachibana ,  Kenichi Yamaguchi

IPC: C23F1/02 ,  H05K3/00 ,  H05K3/06 ,  H05K3/42 ,  B44C1/22 ,  C23F1/00

CPC classification number: H05K3/061 ,  C23F1/02 ,  H05K2201/09581 ,  H05K2203/0582 ,  H05K2203/0591 ,  H05K2203/0769 ,  H05K2203/0786 ,  H05K2203/124 ,  H05K3/0094 ,  H05K3/427

Abstract: Copper through-hole printed wiring boards are produced by forming an etching resist layer on the copper plating of a double sided copper clad laminate. The etching resist layer is formed after a negative resist pattern is applied to both sides of the laminate, and the laminate then dipped in a solution containing at least one salt of 2-alkylbenzimidazoles, 2-alkylalkylbenzimidazoles, 2-phenyl-benzimidazoles and 2-phenylalkylbenzimidazoles. After the resulting etching resist layer is selectively removed with an alkaline aqueous solution, in accordance with the predetermined pattern of the wiring, the exposed copper plating is etched off with an alkali etchant. According to the process of the present invention, remarkable advantages such as increased productivity, lower production costs, reduced toxic substances in waste water, and a high reliability can be obtained in the production of copper through-hole printed wiring boards.

Abstract translation: 通过在双面覆铜层压板的镀铜上形成抗蚀剂层来制造铜通孔印刷线路板。 在将抗蚀剂图案施加到层叠体的两面之后形成抗蚀剂层，然后将层压体浸入含有2-烷基苯并咪唑，2-烷基烷基苯并咪唑，2-苯基 - 苯并咪唑和2-苯基 - 苯并咪唑的至少一种盐的溶液中， 苯基烷基苯并咪唑。 在用碱性水溶液选择性地除去所得到的抗蚀剂层之后，根据布线的预定图案，用碱蚀刻剂蚀刻暴露的镀铜层。 根据本发明的方法，在铜通孔印刷电路板的制造中可以获得诸如提高生产率，降低生产成本，减少废水中有毒物质的降低和高可靠性等显着优点。

公开(公告)号：US5153024A

公开(公告)日：1992-10-06

申请号：US616453

申请日：1990-11-20

Applicant: Jan A. J. Schutyser

Inventor： Jan A. J. Schutyser

IPC: H05K1/03 ,  C08G73/02 ,  C23C18/20 ,  H05K3/18 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

CPC classification number: C08G73/0213 ,  C23C18/2013 ,  C23C18/2086 ,  C23C18/22 ,  C23C18/30 ,  H05K3/381 ,  H05K3/387 ,  H05K2201/09581 ,  H05K2203/1105 ,  H05K2203/122 ,  H05K3/181 ,  H05K3/184 ,  H05K3/422 ,  H05K3/426

Abstract: A process for the manufacture of a multilayer printed circuit board including the step of depositing a noble metal onto an electrically non-conducting substrate. The substrate is first coated with a layer of polyamine polymer modified by being contacted with a compound containing at least two functional groups reactive to amino groups. The coated substrate is then contacted with noble metal ions.

公开(公告)号：US5093761A

公开(公告)日：1992-03-03

申请号：US495158

申请日：1990-03-19

Applicant: Risuke Ozaki

Inventor： Risuke Ozaki

IPC: H05K1/14 ,  H05K3/00 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46

CPC classification number: H05K3/4691 ,  H05K3/445 ,  H05K3/4641 ,  H05K2201/09109 ,  H05K2201/09581 ,  H05K2201/096 ,  H05K2201/2009 ,  H05K2203/1438 ,  H05K3/0061 ,  H05K3/429 ,  Y10S428/901

Abstract: A circuit board device includes a flexible circuit board, a rigid circuit board bonded to at least a part of the flexible circuit board, and a metal plate bonded to at least one of the rigid circuit board and a portion of the flexible circuit board which is itself bonded to the rigid circuit board. Heat generated from components mounted on the rigid circuit board is dissipated through the metal plate to a frame, for example.

Abstract translation: 电路板装置包括柔性电路板，与柔性电路板的至少一部分结合的刚性电路板，以及与刚性电路板和挠性电路板的至少一个接合的金属板， 本身粘接到刚性电路板上。 例如，通过金属板将安装在刚性电路板上的部件产生的热量散发到框架。

公开(公告)号：US5065227A

公开(公告)日：1991-11-12

申请号：US533262

申请日：1990-06-04

Applicant: Jerome A. Frankeny ,  Richard F. Frankeny ,  Karl Hermann ,  Ronald L. Imken

Inventor： Jerome A. Frankeny ,  Richard F. Frankeny ,  Karl Hermann ,  Ronald L. Imken

IPC: H01L21/60 ,  H01L21/66 ,  H01L23/14 ,  H01L23/373 ,  H01L23/498 ,  H05K1/00 ,  H05K3/42 ,  H05K3/44

CPC classification number: H05K3/429 ,  H01L23/142 ,  H01L23/3735 ,  H01L23/4985 ,  H05K3/445 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01078 ,  H05K1/0393 ,  H05K2201/0154 ,  H05K2201/068 ,  H05K2201/09581 ,  H05K2201/09718 ,  H05K2201/09881 ,  H05K2203/0323 ,  H05K2203/1438 ,  Y10T29/41

Abstract: A multilayer, flexible substrate upon which integrated circuit chips can be attached is disclosed. The input/output(I/O) connections from the chip do not radiate outward from the side of the die, but rather extend from a bottom surface. Since the I/O signal lines would not be accessible for testing once the IC chip is mounted on a substrate, each I/O line is extended outward from the IC footprint to an area on the substrate which is accessible. Additionally, an electrical path from each I/O signal port is simultaneously passed through the substrate layers upon which the chip is mounted, thus providing electrical contact of all I/O ports to the underside of the flexible substrate.An integrated circuit chip is mounted on this flexible substrate. Since each I/O line is accessible after mounting, the IC chip can be tested prior to mounting on its ultimate carrier. Once tested, the IC chip and the substrate upon which it is mounted are excised from the roll of substrate material. This excised, pretested memory package, which includes both the IC chip and the flexible substrate, can then be mounted directly onto the ultimate carrier either by reflow soldering or direct bonding.

Abstract translation: 公开了可以连接集成电路芯片的多层柔性基板。 来自芯片的输入/输出（I / O）连接不会从模具侧向外辐射，而是从底部表面延伸。 由于一旦将IC芯片安装在基板上，I / O信号线将无法进行测试，因此每个I / O线从IC占位区向外延伸到可访问的基板上的区域。 此外，来自每个I / O信号端口的电路同时通过其上安装有芯片的基板层，从而提供所有I / O端口与柔性基板的下侧的电接触。 集成电路芯片安装在该柔性基板上。 由于每个I / O线在安装后都可以访问，因此IC芯片可以在安装在其最终的载波上进行测试。 一旦被测试，将IC芯片及其安装在其上的基板从基板材料卷上切下。 包括IC芯片和柔性基板的切除的预测试存储器封装可以通过回流焊接或直接接合直接安装在极限载体上。

公开(公告)号：US5044074A

公开(公告)日：1991-09-03

申请号：US495740

申请日：1990-03-16

Applicant: Helmut Hadwiger ,  Hans Schmidt

Inventor： Helmut Hadwiger ,  Hans Schmidt

IPC: B32B15/08 ,  H05K1/00 ,  H05K1/05 ,  H05K3/38 ,  H05K3/44

CPC classification number: H05K3/445 ,  B32B15/08 ,  H05K1/056 ,  H05K1/0393 ,  H05K2201/0195 ,  H05K2201/09118 ,  H05K2201/09581 ,  H05K2203/1327 ,  H05K2203/1438 ,  H05K3/386 ,  Y10T29/49158 ,  Y10T428/31681 ,  Y10T428/31692 ,  Y10T428/31721

Abstract: A method for the manufacturing of a metal core pc board which provides for manufacturing of two or three dimensional metal core pc boards of any form. The manufacturing of such pc boards can occur by injection molding, injection/compression methods or by a pressing method. High-heat resistant thermoplastics, as well as thermoset plastics are preferably used as pc board materials. A metal with good thermal conductibility is used for the core. The material is selected such that the thermal expansion coefficients of the metal core and the pc board material are optimally equal. The manufacturing contains the following steps: lamination of the metal plate with a plastic foil on one or both sides; placing of such prepared metal core in an injection molding tool; and thermoforming the plastic on the laminated core over the plastic foil.

公开(公告)号：US4983252A

公开(公告)日：1991-01-08

申请号：US335827

申请日：1989-04-10

Applicant: Katsue Masui ,  Isao Kobayashi ,  Shigeru Kubota ,  Toshimoto Moriwaki

Inventor： Katsue Masui ,  Isao Kobayashi ,  Shigeru Kubota ,  Toshimoto Moriwaki

IPC: C23F1/00 ,  G03F7/16 ,  H05K3/00 ,  H05K3/06

CPC classification number: G03F7/168 ,  G03F7/161 ,  H05K3/064 ,  H05K2201/09581 ,  H05K2203/092 ,  H05K2203/107 ,  H05K2203/135 ,  H05K3/0094 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: In a process for fabricating a printed circuit board, a positive resist layer is electrodeposited on a copper clad laminate to ensure that the walls of through-holes in the substrate are completely coated with the resist, or alternatively, a film having a positive resist layer coated thereon is thermocompressed onto the copper clad laminate with the film being in contract with the latter, so as to cover both top and bottom of each through-hole. By subsequent treatments including resist exposure, development, copper foil etching and resist stripping, a high-density wiring pattern can be formed on the substrate in a uniform and consistent way even if through-holes exist in the substrate.

Abstract translation: 在制造印刷电路板的工艺中，将正性抗蚀剂层电沉积在覆铜层压板上，以确保基板中的通孔壁被抗蚀剂完全涂覆，或者替代地，具有正性抗蚀剂层 将其上涂覆有热压到覆铜层压板上，其中膜与后者收缩，以便覆盖每个通孔的顶部和底部。 通过随后的处理，包括抗蚀剂曝光，显影，铜箔蚀刻和抗蚀剂剥离，即使衬底中存在通孔，也可以以均匀且一致的方式在衬底上形成高密度布线图案。