公开(公告)号：US20130043063A1

公开(公告)日：2013-02-21

申请号：US13642471

申请日：2011-03-02

Applicant: Yoichi Saito ,  Shigeru Michiwaki ,  Noriaki Taneko ,  Shukichi Takii

Inventor： Yoichi Saito ,  Shigeru Michiwaki ,  Noriaki Taneko ,  Shukichi Takii

IPC: B32B38/10 ,  H05K1/02 ,  B32B38/08

CPC classification number: H05K3/205 ,  H05K3/26 ,  H05K2201/0376 ,  H05K2201/098 ,  H05K2203/0152 ,  H05K2203/025 ,  H05K2203/1572

Abstract: A method of producing a printed circuit board includes: forming a metal layer on a support plate; forming a mask layer on the metal layer; forming a pattern plating having a stem as plating up to a level of the mask layer, and a cap as a portion of plating exceeding the mask layer and having an outgrowth lying over the surface of the mask layer; laminating an insulating base on a conductive circuit board constituted by the support plate, the metal layer and the pattern plating to form a circuit board intermediate in which the pattern plating is buried in the base; removing the support plate and the metal layer to form an exposed surface; and mechanically polishing the exposed surface until the stem of the pattern plating is removed, to increase the width of the conductive pattern on the exposed surface.

Abstract translation: 制造印刷电路板的方法包括：在支撑板上形成金属层; 在所述金属层上形成掩模层; 形成具有作为所述掩模层的水平的电极的杆的图案电镀，以及超过所述掩模层并且具有位于所述掩模层的表面上的生长的作为电镀部分的帽; 在由支撑板，金属层和图案电镀构成的导电电路板上层叠绝缘基底，以形成电路板中间，其中图案电镀埋在基座中; 移除支撑板和金属层以形成暴露表面; 并且机械抛光露出的表面，直到去除图案电镀的杆，以增加暴露表面上的导电图案的宽度。

公开(公告)号：US08225502B2

公开(公告)日：2012-07-24

申请号：US12102303

申请日：2008-04-14

Applicant: Kentaro Kaneko

Inventor： Kentaro Kaneko

IPC: H01K3/10

CPC classification number: H01L21/486 ,  H01L21/4857 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/48227 ,  H01L2224/81801 ,  H01L2224/85444 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/108 ,  H05K3/205 ,  H05K3/382 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/098 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and a first electrode pad 130 is formed on a chip mounting side. A taper surface 132 of the first electrode pad 130 has a gradient in an orientation reduced in an upward direction toward a solder connecting side or a chip mounting side. Therefore, a holding force for a force applied to the solder connecting side or the chip mounting side is increased, and furthermore, the taper surface 132 adheres to a tapered internal wall of an insulating layer of a first layer so that a bonding strength to the insulating layer is increased.

Abstract translation: 半导体器件100具有半导体芯片110倒装芯片安装在布线板120上的结构。布线板120具有布置多个布线层和多​​个绝缘层的多层结构，并且 第一电极焊盘130形成在芯片安装侧。 第一电极焊盘130的锥形表面132具有沿向上朝向焊接连接侧或芯片安装侧减小的取向的梯度。 因此，施加到焊料连接侧或芯片安装侧的力的保持力增大，此外，锥形表面132粘附到第一层的绝缘层的锥形内壁，使得与 绝缘层增加。

公开(公告)号：US08207018B2

公开(公告)日：2012-06-26

申请号：US12903482

申请日：2010-10-13

Applicant: Horst Theuss ,  Adolf Koller

Inventor： Horst Theuss ,  Adolf Koller

IPC: H01L21/00

CPC classification number: H05K3/3442 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L29/0657 ,  H01L2224/02371 ,  H01L2224/035 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/05556 ,  H01L2224/05568 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/29035 ,  H01L2224/29111 ,  H01L2224/32105 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10156 ,  H05K2201/098 ,  H05K2201/10727 ,  Y02P70/613 ,  H01L2224/05552

Abstract: A semiconductor package is disclosed. One embodiment provides a semiconductor package singulated from a wafer includes a chip defining an active surface, a back side opposite the active surface, and peripheral sides extending between the active surface and the back side; a contact pad disposed on the active surface; and a metallization layer extending from the contact pad onto a portion of the peripheral sides of the chip.

Abstract translation: 公开了半导体封装。 一个实施例提供了从晶片单个化的半导体封装，其包括限定有源表面的芯片，与有源表面相对的后侧，以及在有源表面和背面之间延伸的周边; 设置在所述活动表面上的接触垫; 以及从接触垫延伸到芯片周边的一部分上的金属化层。

公开(公告)号：US08168891B1

公开(公告)日：2012-05-01

申请号：US12151088

申请日：2008-05-02

Applicant: Joel R. Goergen ,  Yi Zheng

Inventor： Joel R. Goergen ,  Yi Zheng

IPC: H05K1/00

CPC classification number: H05K1/0216 ,  B32B2305/076 ,  B32B2309/08 ,  B32B2457/08 ,  H01P3/081 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/0366 ,  H05K3/0091 ,  H05K3/46 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/029 ,  H05K2201/09236 ,  H05K2201/09745 ,  H05K2201/098 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.

公开(公告)号：US20120048600A1

公开(公告)日：2012-03-01

申请号：US12870072

申请日：2010-08-27

Applicant: Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

Inventor： Matthew S. Doyle ,  Joseph Kuczynski ,  Kevin A. Splittstoesser ,  Timothy J. Tofil

IPC: H05K1/03 ,  C25D7/00 ,  G03F7/20 ,  G06F17/50 ,  B05D5/12

CPC classification number: H05K1/0296 ,  C25D5/022 ,  C25D5/10 ,  C25D7/00 ,  H05K1/0245 ,  H05K3/18 ,  H05K3/184 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/056 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A first artwork layer having a first adaptable-mask section allows a graded amount of light to pass into an underlying first photoresist layer. Subsequent to developing the first photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a lower portion of a rounded trace. A dielectric layer is laminated upon the lower portion and a second artwork layer having an second adaptable-mask section allows a graded amount of light to pass into a second photoresist layer. Subsequent to developing the second photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least an upper portion of a rounded trace. The photoresist and dielectric layers are removed resulting in a circuit apparatus having a rounded differential pair trace.

Abstract translation: 具有第一适应性掩模部分的第一艺术品层允许渐变量的光进入下面的第一光致抗蚀剂层。 在显影第一光致抗蚀剂层之后，分级的光产生用作模具或侧壁的圆形几何空隙，用于产生圆形迹线的至少下部。 电介质层层叠在下部，具有第二可适应掩模部分的第二艺术品层允许渐变量的光通过第二光致抗蚀剂层。 在显影第二光致抗蚀剂层之后，分级的光产生用作模具或侧壁的圆形几何空隙，用于至少形成圆形迹线的上部。 去除光致抗蚀剂和介电层，导致具有圆形差分对迹线的电路设备。

公开(公告)号：US08008756B2

公开(公告)日：2011-08-30

申请号：US12300184

申请日：2007-06-13

Applicant: Tetsuya Tsumura ,  Hiroharu Nishiyama ,  Etsuo Tsujimoto

Inventor： Tetsuya Tsumura ,  Hiroharu Nishiyama ,  Etsuo Tsujimoto

IPC: H01L23/495

CPC classification number: H05K3/202 ,  H01L23/3737 ,  H01L23/49861 ,  H01L24/81 ,  H01L2924/12042 ,  H01L2924/15747 ,  H05K1/0373 ,  H05K1/056 ,  H05K3/027 ,  H05K3/06 ,  H05K2201/0209 ,  H05K2201/0376 ,  H05K2201/09118 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2201/10106 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A heat dissipating wiring board includes a metal wiring plate with a circuit pattern formed therein, a filler containing resin layer embedded with the metal wiring plate such that a top surface of the metal wiring plate is exposed, and a heat dissipating plate arranged on an under surface of the filler containing resin layer. The circuit pattern is formed of a through groove provided in the metal wiring plate. The through groove includes a fine groove that opens at the top surface of the metal wiring plate and an expanded groove that expands from a lower end of the fine groove toward the under surface of the metal wiring plate. The heat dissipating wiring board is capable of improving reliability against electric insulation due to dust or the like in a space of the through groove.

Abstract translation: 一种散热布线板包括其中形成有电路图案的金属布线板，嵌入有金属布线板的填料容纳树脂层，以使金属布线板的上表面露出;以及布置在下面的散热板 填料含树脂层的表面。 电路图案由设置在金属布线板中的贯通槽形成。 贯通槽包括在金属配线板的上表面开口的细槽，以及从金属配线板的下表面向微细槽的下端扩展的扩径槽。 散热布线板能够提高通过沟槽的空间中的灰尘等导致的电绝缘性的可靠性。

公开(公告)号：US20110088842A1

公开(公告)日：2011-04-21

申请号：US12961610

申请日：2010-12-07

Applicant: JOEL R. GOERGEN ,  Yi Zheng

Inventor： JOEL R. GOERGEN ,  Yi Zheng

IPC: B32B37/04

CPC classification number: H05K1/0216 ,  B32B2305/076 ,  B32B2309/08 ,  B32B2457/08 ,  H01P3/081 ,  H05K1/024 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0298 ,  H05K1/0366 ,  H05K3/0091 ,  H05K3/46 ,  H05K3/4611 ,  H05K2201/0187 ,  H05K2201/029 ,  H05K2201/09236 ,  H05K2201/09745 ,  H05K2201/098 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.

Abstract translation: 公开了电路板及其制造方法。 电路板使用形成为包括纵向通道的导体承载高速信号。 通道增加了导体的表面积，从而增强了导体承载高速信号的能力。 在至少一些实施例中，通道内的介电常数和通道之外的介质常数之间也存在不连续性，这被认为可减少信号损耗。

公开(公告)号：US20100282501A1

公开(公告)日：2010-11-11

申请号：US12840751

申请日：2010-07-21

Applicant: Tomofumi KITADA ,  Hiroki MARUO ,  Ryo TAKAMI

Inventor： Tomofumi KITADA ,  Hiroki MARUO ,  Ryo TAKAMI

IPC: H05K1/09 ,  H05K1/11

CPC classification number: H05K3/363 ,  H01L2924/0002 ,  H05K2201/09745 ,  H05K2201/098 ,  H05K2201/09845 ,  H01L2924/00

Abstract: A board interconnection structure having a first printed wiring board in which a first conductive circuit is arranged on a first insulating layer, the first conductive circuit having, on an end portion thereof, a first connection terminal in which an upper surface width is narrower than a bottom surface width; a second printed wiring board in which a second conductive layer having a second connection terminal is arranged on a second insulating layer; and a connection layer that forms fillets along longitudinal side surfaces of the first connection terminal, and interconnects the first connection terminal and the second connection terminal. The first connection terminal may have a projection portion.

Abstract translation: 一种电路板互连结构，具有第一印刷线路板，其中第一导电电路布置在第一绝缘层上，所述第一导电电路在其端部上具有第一连接端子，其中上表面宽度窄于 底面宽度; 第二印刷线路板，其中具有第二连接端子的第二导电层布置在第二绝缘层上; 以及连接层，其沿着所述第一连接端子的纵向侧表面形成圆角，并且将所述第一连接端子和所述第二连接端子互连。 第一连接端子可以具有突出部分。

公开(公告)号：US07829265B2

公开(公告)日：2010-11-09

申请号：US12244870

申请日：2008-10-03

Applicant: Tomofumi Kitada ,  Hiroki Maruo ,  Ryo Takami

Inventor： Tomofumi Kitada ,  Hiroki Maruo ,  Ryo Takami

IPC: G03F7/00 ,  G03F7/40 ,  G03F7/26

CPC classification number: H05K3/363 ,  H01L2924/0002 ,  H05K2201/09745 ,  H05K2201/098 ,  H05K2201/09845 ,  H01L2924/00

Abstract: A board interconnection structure having a first printed wiring board in which a first conductive circuit is arranged on a first insulating layer, the first conductive circuit having, on an end portion thereof, a first connection terminal in which an upper surface width is narrower than a bottom surface width; a second printed wiring board in which a second conductive layer having a second connection terminal is arranged on a second insulating layer; and a connection layer that forms fillets along longitudinal side surfaces of the first connection terminal, and interconnects the first connection terminal and the second connection terminal. The first connection terminal may have a projection portion.

Abstract translation: 一种电路板互连结构，具有第一印刷线路板，其中第一导电电路布置在第一绝缘层上，所述第一导电电路在其端部上具有第一连接端子，其中上表面宽度窄于 底面宽度; 第二印刷线路板，其中具有第二连接端子的第二导电层布置在第二绝缘层上; 以及连接层，其沿着所述第一连接端子的纵向侧表面形成圆角，并且将所述第一连接端子和所述第二连接端子互连。 第一连接端子可以具有突出部分。

公开(公告)号：US07804031B2

公开(公告)日：2010-09-28

申请号：US11763861

申请日：2007-06-15

Applicant: Toru Nakai ,  Masanori Tamaki

Inventor： Toru Nakai ,  Masanori Tamaki

IPC: H05K1/03

CPC classification number: H05K1/0242 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0216 ,  H05K1/0245 ,  H05K3/28 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/098

Abstract: A printed wiring board having an interlayer insulation layer and conductive circuits formed on the interlayer insulation layer. The conductive circuits include a first conductive circuit and a second conductive circuit positioned adjacent to each other, and the first and second conductive circuits satisfy a formula, 0.10 T≦|W1−W2|≦0.73 T, where W1 represents an upper conductive circuit space between the first and second conductive circuits, W2 represents a lower conductive circuit space between the first and second conductive circuits, and T represents a thickness of the first and second conductive circuits.

Abstract translation: 一种具有层间绝缘层和形成在层间绝缘层上的导电电路的印刷电路板。 导电电路包括彼此相邻定位的第一导电电路和第二导电电路，第一和第二导电电路满足公式0.10 T＆nlE; | W1-W2 |＆nlE; 0.73T，其中W1表示上导电电路 第一和第二导电电路之间的间隔W2表示第一和第二导电电路之间的较低的导电电路空间，T表示第一和第二导电电路的厚度。