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公开(公告)号：US20190029113A1
公开(公告)日：2019-01-24
申请号：US16116156
申请日：2018-08-29
Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Inventor： Masahiro Kyozuka
IPC: H05K1/14 , H01L23/31 , H01L23/538 , H01L25/00 , H01L25/10
CPC classification number: H05K1/144 , H01L21/486 , H01L23/3121 , H01L23/3135 , H01L23/49811 , H01L23/5384 , H01L23/5385 , H01L23/5389 , H01L25/0655 , H01L25/105 , H01L25/50 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/1533 , H01L2924/18161 , H05K2201/042 , H05K2201/10242
Abstract: An electronic component device includes a cored wiring substrate, an electronic component, a reinforcing layer, a connection terminal, and sealing resin. The cored wiring substrate includes a core layer. The electronic component is mounted on the cored wiring substrate. The coreless wiring substrate is disposed on the cored wiring substrate and the electronic component. The reinforcing layer is provided in the coreless wiring substrate and in a region corresponding to the electronic component. The connection terminal connects the cored wiring substrate and the coreless wiring substrate. The sealing resin is filled between the cored wiring substrate and the coreless wiring substrate.
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公开(公告)号：US20180220521A1
公开(公告)日：2018-08-02
申请号：US15421709
申请日：2017-02-01
Applicant: Cisco Technology, Inc.
Inventor： Phil Slight , Vic Chia
CPC classification number: H01L23/4006 , H01L2023/4062 , H01L2023/4081 , H01L2023/4087 , H05K1/0203 , H05K1/0209 , H05K7/2049 , H05K2201/066 , H05K2201/10242 , H05K2201/10265 , H05K2201/10393 , H05K2201/10409
Abstract: A circuit board includes a heatsink configured to be coupled to the circuit board via a first coupling mechanism, the first coupling mechanism providing an asymmetrical downward force for coupling the heatsink to the circuit board. The circuit board further includes a second coupling mechanism configured to provide a counter force to the asymmetrical downward force of the first coupling mechanism. The counter force can be configured on an overhang portion of the heatsink that does not cover a circuit on the circuit board.
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公开(公告)号：US10006787B2
公开(公告)日：2018-06-26
申请号：US15155764
申请日：2016-05-16
Applicant: ScienBiziP Consulting (Shenzhen) Co., Ltd.
Inventor： Tsung-Ju Wu , Jen-Tsorng Chang , Hsin-Pei Hsieh , Yi-Cheng Lin
CPC classification number: G01D11/30 , G06F3/0414 , H05K1/0393 , H05K1/144 , H05K1/16 , H05K1/181 , H05K3/284 , H05K2201/042 , H05K2201/05 , H05K2201/10151 , H05K2201/10242 , Y02P70/611
Abstract: A high density sensor module includes a first substrate, a plurality of first sensors positioned on the first substrate, a plurality of first conductive rods positioned on the corresponding first sensors, a first package resin member covering the first sensors and one end of each of the first conductive rods, a second substrate positioned on the first package resin member, a plurality of second sensors positioned on the second substrate, and a second package resin member covering the second sensors and another end of each of the first conductive rods. The first conductive rods pass through the first package resin member and the second substrate. The high density sensor module has a two-layer structure to increase the number of the sensors such that the sensing density and resolution of the high-density sensor module are increased.
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公开(公告)号：US20180090860A1
公开(公告)日：2018-03-29
申请号：US15118872
申请日：2016-06-21
Inventor： Xiaoyu HUANG
CPC classification number: H01R12/585 , G02F1/1333 , G02F1/13452 , G02F1/136204 , H01R12/57 , H05F3/02 , H05K1/0215 , H05K3/0061 , H05K3/325 , H05K7/02 , H05K2201/10242 , H05K2201/1059 , H05K2201/2036
Abstract: The present disclosure relates to a display device including a backplate made by metallic material, a fixing pillar, a flexible conductive layer, and a PCB. The fixing pillar includes a limiting portion, a fixing portion, and a connecting portion connected in sequence, and the connecting portion connects to the backplate. The flexible conductive layer sheathes a rim of the fixing, and the flexible conductive layer includes a first side and a second side opposite to the first side, and the second side connects to the backplate. The PCB connects between the limiting portion and the first side, and an area of the first side connected by the PCB includes a first ground area for electrically connecting to the backplate via the flexible conductive layer. The PCB of the display device may effectively reduce the electrostatic interference.
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公开(公告)号：US09907180B2
公开(公告)日：2018-02-27
申请号：US14737645
申请日：2015-06-12
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Yoshihito Otsubo , Nobuaki Ogawa
IPC: H05K1/11 , H05K1/18 , H01L25/065 , H05K3/36 , H05K3/46 , H05K1/02 , H05K1/14 , H01L23/31 , H01L25/16 , H05K3/28
CPC classification number: H05K1/183 , H01L23/3121 , H01L25/0657 , H01L25/16 , H01L2224/16225 , H01L2225/06517 , H01L2225/0652 , H01L2225/06572 , H01L2924/1531 , H01L2924/19105 , H05K1/0298 , H05K1/144 , H05K3/284 , H05K3/36 , H05K3/4614 , H05K2201/042 , H05K2201/10242 , H05K2203/0156 , H05K2203/1316 , H05K2203/1327 , Y10T29/49124
Abstract: The present disclosure enhances the design flexibility of a multilayer electronic device. A multilayer electronic device is formed by alternately stacking, in a top-bottom direction, substrate layers in which substrates are disposed and a component layer in which at least one component is disposed. A non-superposing region in which a substrate of a first substrate layer positioned on the upper side of a first component layer is not superposed on a substrate of a second substrate layer positioned on the lower side of the first component layer, as viewed from above, is formed in the substrate. Accordingly, within the multilayer electronic device, a space in which the substrate of the second substrate layer is not located can be formed in a region under the non-superposing region of the substrate of the first substrate layer. By using this space, the design flexibility of the multilayer electronic device can be enhanced.
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Patent Agency Ranking
86.发明申请公开(公告)号：US20170311451A1
公开(公告)日：2017-10-26
申请号：US15641057
申请日：2017-07-03
Applicant: Quartzdyne, Inc.
Inventor： Mark Hahn
CPC classification number: H05K3/103 , B23K9/0043 , B23K9/091 , B23K9/092 , B23K9/167 , B23K9/23 , B23K26/0622 , B23K26/21 , B23K26/22 , B23K26/32 , B23K2101/38 , B23K2103/00 , H01L23/49811 , H01L24/02 , H01L24/05 , H01L24/07 , H01L24/08 , H01L24/09 , H01L24/42 , H01L24/44 , H01L24/45 , H01L24/46 , H01L24/48 , H01L24/85 , H01L2224/02163 , H01L2224/02185 , H01L2224/04042 , H01L2224/45147 , H01L2224/45639 , H01L2224/48476 , H01L2224/80007 , H01L2224/80009 , H01L2224/8019 , H01L2224/8034 , H01L2924/00014 , H05K1/18 , H05K3/328 , H05K2201/10242 , H05K2201/10265 , H05K2201/10287 , H01L2224/05599 , H01L2224/85399
Abstract: A method of forming a microelectronic device structure comprises coiling a portion of a wire up and around at least one sidewall of a structure protruding from a substrate. At least one interface between an upper region of the structure and an upper region of the coiled portion of the wire is welded to form a fused region between the structure and the wire.
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公开(公告)号：US09786331B1
公开(公告)日：2017-10-10
申请号：US15220175
申请日：2016-07-26
Applicant: Western Digital Technologies, Inc.
Inventor： Albert John Wallash
CPC classification number: G11B33/1493 , G06F1/182 , H01P1/2039 , H01P3/026 , H05K1/0219 , H05K1/0224 , H05K1/0225 , H05K1/0227 , H05K1/0245 , H05K1/0253 , H05K2201/0715 , H05K2201/09309 , H05K2201/09363 , H05K2201/09618 , H05K2201/09672 , H05K2201/09781 , H05K2201/10242 , H05K2201/2072
Abstract: The present disclosure generally relates to a shielded three-layer patterned ground structure in a PCB. The PCB may be disposed in a hard disk drive. To reduce costs, PCBs are being made with only four total layers separated by dielectric material. Conductive traces in PCBs can have the problem of common mode current flowing through the traces and thus increasing the magnitude of EMI noise. By providing a shielded three-layer patterned ground structure, not only is the cost reduced, but so is the common mode current and the magnitude of EMI noise, all without any negative impact to the differential signal.
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公开(公告)号：US20170254680A1
公开(公告)日：2017-09-07
申请号：US15155764
申请日：2016-05-16
Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
Inventor： TSUNG-JU WU , JEN-TSORNG CHANG , HSIN-PEI HSIEH , YI-CHENG LIN
CPC classification number: G01D11/30 , G06F3/0414 , H05K1/0393 , H05K1/144 , H05K1/16 , H05K1/181 , H05K3/284 , H05K2201/042 , H05K2201/05 , H05K2201/10151 , H05K2201/10242 , Y02P70/611
Abstract: A high density sensor module includes a first substrate, a plurality of first sensors positioned on the first substrate, a plurality of first conductive rods positioned on the corresponding first sensors, a first package resin member covering the first sensors and one end of each of the first conductive rods, a second substrate positioned on the first package resin member, a plurality of second sensors positioned on the second substrate, and a second package resin member covering the second sensors and another end of each of the first conductive rods. The first conductive rods pass through the first package resin member and the second substrate. The high density sensor module has a two-layer structure to increase the number of the sensors such that the sensing density and resolution of the high-density sensor module are increased.
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公开(公告)号：US20170208704A1
公开(公告)日：2017-07-20
申请号：US15358687
申请日：2016-11-22
Applicant: MDM Inc.
Inventor： Ku Yong KIM
CPC classification number: H05K7/209 , H05K1/0204 , H05K1/0207 , H05K1/021 , H05K1/0263 , H05K1/181 , H05K3/0061 , H05K3/303 , H05K3/4608 , H05K2201/09054 , H05K2201/10166 , H05K2201/10242
Abstract: The present disclosure relates to a layered structure of a multi-layer PCB, and more particularly, to a structure of a high-power multi-layer PCB which can use a high current by efficiently dissipating heat generated from the inside of the multi-layered PCB and heat generated from a power semiconductor module package mounted on the PCB, and a production method thereof. The multi-layer PCB includes: a conductive plate having a plurality of heat poles protruding from at least one of a top surface and a bottom surface thereof; PCBs which are disposed on the top surface and the bottom surface of the conductive plate, and have a plurality of penetrating holes formed therethrough to allow the heat poles of the conductive plate to be inserted thereinto; and an insulation layer which is attached between the conductive plate and the PCBs in order to electrically insulate.
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公开(公告)号：US20170208695A1
公开(公告)日：2017-07-20
申请号：US15459383
申请日：2017-03-15
Applicant: Massachusetts Institute of Technology
Inventor： Glenn A. Brigham , Richard J. Stanley , Bradley Thomas Perry , Patrick J. Bell
CPC classification number: H05K3/42 , H05K1/0222 , H05K1/115 , H05K1/116 , H05K3/0094 , H05K3/4685 , H05K2201/0959 , H05K2201/09745 , H05K2201/10242 , H05K2203/03 , H05K2203/0703 , H05K2203/30 , Y10T29/49123
Abstract: A printed circuit board, and a method of fabricating the printed circuit board is disclosed. The printed circuit board includes at least one coaxial via. A hollow via is disposed in the printed circuit board. A metal sleeve is formed around the circumference of said hollow via. An inner conductive path is disposed in the hollow via. Additionally, an insulating material is disposed in the hollow via, between the conducting path and the metal sleeve. The conductive path is used to connect signal traces disposed on two different layers of the printed circuit board. In some embodiments, these signal traces carry signals having a frequency above 1 GHz, although the disclosure is not limited to this embodiment.
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