公开(公告)号：US20230207527A1

公开(公告)日：2023-06-29

申请号：US17564137

申请日：2021-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Wonjun JUNG ,  Jasmeet SINGH NARANG ,  Tyrone HUANG ,  Christopher KLEMENT ,  Alan D. SMITH ,  Edward CHANG ,  John WUU

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L25/0652 ,  H01L2225/06544

Abstract: Integrated circuits and integrated circuit dies include TSVs laid out in symmetrical patterns. Because of the symmetrical arrangement of the TSVs and associated routing patterns, an integrated circuit is able to support operation of multiple similar dies that are placed in different positions in the integrated circuit. This in turn simplifies the design and production of the multiple similar dies, thus reducing development and manufacturing costs for the corresponding integrated circuits.

公开(公告)号：US20250098181A1

公开(公告)日：2025-03-20

申请号：US18829848

申请日：2024-09-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Alan D. SMITH ,  Samuel NAFFZIGER ,  Joe MACRI ,  James R. MAGRO ,  Vydhyanathan KALYANASUNDHARAM

IPC: H10B80/00 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

Abstract: A package device includes a processing device, memory dies and a memory controller. The memory controller die is coupled to the processing device and the memory dies. The memory controller die controls communication from the processing device to the memory dies and to an external memory device. The external memory device is external to the memory dies.

公开(公告)号：US20250149525A1

公开(公告)日：2025-05-08

申请号：US18615918

申请日：2024-03-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Deepak Vasant KULKARNI ,  Alan D. SMITH ,  Raja SWAMINATHAN

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L23/538 ,  H10B80/00

Abstract: Disclosed herein are chip packages and electronic devices that utilized an active silicon bridge having a memory controller to interface between a logic device having at least one compute die and one or more memory stacks within a singular chip package. In one example, a chip package is provided that includes a substrate, a logic device, a memory stack, and an active silicon bridge. The logic device is disposed over the substrate. The logic device includes one or more compute dies. The memory stack is disposed over the substrate adjacent the logic device. The active silicon bridge has a first portion and a second portion. The first portion is disposed between the substrate and the logic device, while the second portion is disposed between the substrate and the memory stack.

公开(公告)号：US20230195664A1

公开(公告)日：2023-06-22

申请号：US17558798

申请日：2021-12-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Sean KEELY ,  Joseph L. GREATHOUSE ,  Hari THANGIRALA ,  Alan D. SMITH ,  Milind N. NEMLEKAR

IPC: G06F13/28 ,  G06F13/16

CPC classification number: G06F13/28 ,  G06F13/1668

Abstract: A method for software management of DMA transfer commands includes receiving a DMA transfer command instructing a data transfer by a first processor device. Based at least in part on a determination of runtime system resource availability, a device different from the first processor device is assigned to assist in transfer of at least a first portion of the data transfer. In some embodiments, the DMA transfer command instructs the first processor device to write a copy of data to a third processor device. Software analyzes network bus congestion at a shared communications bus and initiates DMA transfer via a multi-hop communications path to bypass the congested network bus.

公开(公告)号：US20250118719A1

公开(公告)日：2025-04-10

申请号：US18752735

申请日：2024-06-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Brett P. WILKERSON ,  Alan D. SMITH

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/053 ,  H01L23/498 ,  H01L23/528 ,  H01L25/00 ,  H10B80/00

Abstract: Disclosed herein are chip packages that integrate multiple compute dies through a single interposer die to a memory stack. The interposer die includes memory controller circuitry that allowing multiple compute dies to access the memory stack in an efficient manner.

公开(公告)号：US20240419358A1

公开(公告)日：2024-12-19

申请号：US18665840

申请日：2024-05-16

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Joseph L. GREATHOUSE ,  Sean KEELY ,  Alan D. SMITH ,  Anthony ASARO ,  Ling-Ling WANG ,  Milind N NEMLEKAR ,  Hari THANGIRALA ,  Felix KUEHLING

IPC: G06F3/06 ,  G06F13/28

Abstract: A method for hardware management of DMA transfer commands includes accessing, by a first DMA engine, a DMA transfer command and determining a first portion of a data transfer requested by the DMA transfer command. Transfer of a first portion of the data transfer by the first DMA engine is initiated based at least in part on the DMA transfer command. Similarly, a second portion of the data transfer by a second DMA engine is initiated based at least in part on the DMA transfer command. After transferring the first portion and the second portion of the data transfer, an indication is generated that signals completion of the data transfer requested by the DMA transfer command.