公开(公告)号：US20060190642A1

公开(公告)日：2006-08-24

申请号：US11064752

申请日：2005-02-24

Applicant: Alfredo Aldereguia ,  Brian Koehler ,  Grace Richter

Inventor： Alfredo Aldereguia ,  Brian Koehler ,  Grace Richter

IPC: G06F3/06

CPC classification number: G06F11/24

Abstract: A data receiver circuit in a receiving chip provides the capability to characterize an interface, which includes one or more inter-chip communication lines, between a transmitting chip and the receiving chip by transmitting the data across a primary data path and a secondary data path, latching the data in the secondary data path using a clock signal that is skewed relative to a clock signal used to latch the primary data path, comparing the data latched from the primary and secondary data paths, and recording errors. Because the primary data path is not impacted by the test cycle, the test cycle may be run while data associated with applications running on the system are transmitted across the inter-chip communication lines.

公开(公告)号：US20060212263A1

公开(公告)日：2006-09-21

申请号：US10992444

申请日：2004-11-18

Applicant: Brian Koehler ,  Brian Vanderpool

Inventor： Brian Koehler ,  Brian Vanderpool

IPC: G21C17/00

CPC classification number: G06F11/3409 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/88 ,  G06F2201/885

Abstract: A circuit and method for using hardware to calculate a first derivative of the number of performance events that occur in a microprocessor during a predetermined period of time. This first derivative indicates a frequency of such performance events, which can be used as either a predictor of future problems or needs, or may be used to invoke a corrective action.

公开(公告)号：US20060059451A1

公开(公告)日：2006-03-16

申请号：US10941415

申请日：2004-09-15

Applicant: Brian Koehler ,  Robert Shearer ,  Lance Thompson

Inventor： Brian Koehler ,  Robert Shearer ,  Lance Thompson

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: Methods for creating and synthesizing multiple instances of a component from a single logical model are provided. In general, a flag is provided which designates a design methodology for use in instantiating the component. Depending on the value of the flag, a block of hardware design code defining an instance of the component according to a design methodology is loaded.

Abstract translation: 提供了从单个逻辑模型创建和合成组件的多个实例的方法。 通常，提供了一个标志，其指定用于实例化组件的设计方法。 根据标志的值，加载根据设计方法定义组件实例的硬件设计代码块。