公开(公告)号：US20060212263A1

公开(公告)日：2006-09-21

申请号：US10992444

申请日：2004-11-18

Applicant: Brian Koehler ,  Brian Vanderpool

Inventor： Brian Koehler ,  Brian Vanderpool

IPC: G21C17/00

CPC classification number: G06F11/3409 ,  G06F11/3466 ,  G06F2201/81 ,  G06F2201/88 ,  G06F2201/885

Abstract: A circuit and method for using hardware to calculate a first derivative of the number of performance events that occur in a microprocessor during a predetermined period of time. This first derivative indicates a frequency of such performance events, which can be used as either a predictor of future problems or needs, or may be used to invoke a corrective action.

公开(公告)号：US20060123206A1

公开(公告)日：2006-06-08

申请号：US11004199

申请日：2004-12-03

Applicant: Wayne Barrett ,  Brian Vanderpool

Inventor： Wayne Barrett ,  Brian Vanderpool

IPC: G06F13/28

CPC classification number: G06F13/1626

Abstract: Uncontested priority is provided to out-of-order data transfers over in-order data transfers on a data bus shared by a plurality of memory requesters. By always granting priority to out-of-order transfers such as deferred read data transfers over in-order transfers such as write and/or cache-to-cache data transfers, it is assured that no newer command or transaction ever negatively affects the latency of an older command or transaction.

Abstract translation: 无条件优先级被提供给由多个存储器请求者共享的数据总线上的按顺序数据传输的无序数据传输。 通过总是优先处理诸如写入和/或缓存到高速缓存数据传输之类的按顺序传输的延迟读取数据传输的无序传输，确保没有较新的命令或事务对延迟产生负面影响 的旧命令或事务。

公开(公告)号：US20070061519A1

公开(公告)日：2007-03-15

申请号：US11225655

申请日：2005-09-13

Applicant: Wayne Barrett ,  Kenneth Valk ,  Brian Vanderpool

Inventor： Wayne Barrett ,  Kenneth Valk ,  Brian Vanderpool

IPC: G06F13/28

CPC classification number: G06F13/1663 ,  G06F12/0817

Abstract: An early return indication is used to notify a first communications interface, prior to a response being received from any of a plurality of sources coupled to a second communications interface, that the return data can be used by the first communications interface when it is received thereby from a source of the return data if the source has an exclusive copy of the return data. By doing so, the first communications interface can often prepare for forwarding the return data over its associated communication link such that the data can be forwarded with little or no latency once the data is retrieved from its source, and may be able to initiate the return of data over the communication link prior to all responses being received from the other sources. The early return indication may also serves as an early coherency indication in that the first communications interface is no longer required to wait for updating of a coherency directory to complete prior to forwarding the return data over the communication link.

Abstract translation: 早期返回指示用于在从与第二通信接口耦合的多个源中的任一个接收到响应之前通知第一通信接口，使得第一通信接口在接收时可以由第一通信接口使用返回数据 来自返回数据的源，如果源具有返回数据的排他副本。 通过这样做，第一通信接口通常可以准备通过其相关联的通信链路转发返回数据，使得一旦数据从源中检索出来，数据可以很少或没有等待时间转发，并且可能能够启动返回 在从其他来源接收到所有响应之前通过通信链路的数据。 早期返回指示还可以用作早期一致性指示，因为在通过通信链路转发返回数据之前，第一通信接口不再需要等待更新相干性目录来完成。

公开(公告)号：US20060248275A1

公开(公告)日：2006-11-02

申请号：US11116626

申请日：2005-04-28

Applicant: Herman Blackmon ,  Philip Hillier ,  Joseph Kirscht ,  Brian Vanderpool

Inventor： Herman Blackmon ,  Philip Hillier ,  Joseph Kirscht ,  Brian Vanderpool

IPC: G06F12/00

CPC classification number: G06F9/3824 ,  G06F13/1642

Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, select a command to send to memory. In an embodiment, the oldest command in a write queue that does not collide with a conflict queue is sent to memory and added to the conflict queue if some or all of the following are true: all of the commands in the read queue collide with the conflict queue, any read command incoming from the processor does not collide with the write queue, the number of commands in the write queue is greater than a first threshold, and all commands in the conflict queue have been present for less than a second threshold. In an embodiment, a command does not collide with a queue if the command does not access the same cache line in memory as the commands in the queue. In this way, in an embodiment, write commands are sent to the memory at a time that reduces the impact on the performance of read commands.

Abstract translation: 在一个实施例中，选择要发送到存储器的命令的方法，装置，系统和信号承载介质。 在一个实施例中，写入队列中与冲突队列不冲突的最早的命令被发送到存储器，并且如果以下部分或全部为真，则将其添加到冲突队列中：读队列中的所有命令与 冲突队列，从处理器传入的任何读取命令都不会与写入队列冲突，写入队列中的命令数量大于第一个阈值，并且冲突队列中的所有命令都存在少于第二个阈值。 在一个实施例中，如果命令不访问存储器中与队列中的命令相同的高速缓存行，则命令不与队列冲突。 以这种方式，在一个实施例中，写入命令在减少对读取命令的性能的影响的时刻被发送到存储器。

公开(公告)号：US20060143403A1

公开(公告)日：2006-06-29

申请号：US11023706

申请日：2004-12-28

Applicant: Wayne Barrett ,  David Shedivy ,  Kenneth Valk ,  Brian Vanderpool

Inventor： Wayne Barrett ,  David Shedivy ,  Kenneth Valk ,  Brian Vanderpool

IPC: G06F13/00

CPC classification number: G06F12/0817 ,  G06F2212/507

Abstract: In a shared memory architecture, early coherency indication is used to notify a communications interface, prior to the data for a memory request is returned, and prior to updating a coherency directory in response to the memory request, that the return data can be used by the communications interface when it is received thereby from a source of the return data. By doing so, the communications interface can often begin forwarding the return data over its associated communication link with little or no latency once the data is retrieved from its source. In addition, the communications interface is often no longer required to wait for updating of the coherency directory to complete prior to forwarding the return data over the communication link. As such, the overall latency for handling the memory request is typically reduced.

Abstract translation: 在共享存储器架构中，早期一致性指示用于在返回存储器请求的数据之前以及在响应于存储器请求更新一致性目录之前通知通信接口，返回数据可以由 当从返回数据的来源接收通信接口时。 通过这样做，一旦数据从其源中检索，通信接口通常可以在几乎没有或没有延迟的情况下开始转发其相关联的通信链路上的返回数据。 此外，通常不需要通信接口在通过通信链路转发返回数据之前等待更新相干性目录来完成。 因此，处理存储器请求的总体延迟通常减少。

公开(公告)号：US20070083715A1

公开(公告)日：2007-04-12

申请号：US11225656

申请日：2005-09-13

Applicant: Brian Vanderpool

Inventor： Brian Vanderpool

IPC: G06F13/28

CPC classification number: G06F12/0817 ,  G06F12/0828

Abstract: An early return indication is used to notify a first communications interface, prior to a response being received from any of a plurality of sources coupled to a second communications interface, that the return data can be used by the first communications interface when it is received thereby from a source of the return data. By doing so, the first communications interface can often prepare for forwarding the return data over its associated communication link such that the data can be forwarded with little or no latency once the data is retrieved from its source, and may be able to initiate the return of data over the communication link prior to all responses being received from the other sources. The early return indication may also serve as an early coherency indication in that the first communications interface is no longer required to wait for updating of a coherency directory to complete prior to forwarding the return data over the communication link.

Abstract translation: 早期返回指示用于在从与第二通信接口耦合的多个源中的任一个接收到响应之前通知第一通信接口，使得第一通信接口在接收时可以由第一通信接口使用返回数据 从一个来源的返回数据。 通过这样做，第一通信接口通常可以准备通过其相关联的通信链路转发返回数据，使得一旦数据从源中检索出来，数据可以很少或没有等待时间转发，并且可能能够启动返回 在从其他来源接收到所有响应之前通过通信链路的数据。 早期返回指示还可以用作早期一致性指示，因为在通过通信链路转发返回数据之前，第一通信接口不再需要等待更新相干性目录来完成。

公开(公告)号：US20070073974A1

公开(公告)日：2007-03-29

申请号：US11239616

申请日：2005-09-29

Applicant: Duane Averill ,  Brian Vanderpool

Inventor： Duane Averill ,  Brian Vanderpool

IPC: G06F12/00

CPC classification number: G06F12/128 ,  G06F12/0811 ,  G06F2212/2542

Abstract: A cache eviction algorithm for an inclusive cache determines which among a plurality of cache lines may be evicted from the inclusive cache based at least in part upon the state of the cache lines in a higher level cache. In particular, a cache eviction algorithm may determine, from an inclusive cache directory for a lower level cache, whether a cache line is cached in the lower level cache but not cached in any of a plurality of higher level caches for which cache directory information is additionally stored in the cache directory. Then, based upon determining that a cache line is cached in the lower level cache but not cached in any of the plurality of higher level caches, the cache eviction algorithm may select that cache line for eviction from the cache.

Abstract translation: 至少部分地基于高级缓存中的高速缓存行的状态，用于包含性高速缓存的高速缓存驱逐算法确定多个高速缓存行中的哪一个可以从包含的高速缓存中逐出。 特别地，缓存驱逐算法可以从用于较低级别高速缓存的包含性高速缓存目录中确定高速缓存行是否被缓存在较低级高速缓存中，但是不缓存在高速缓存目录信息为多个高级缓存 另外存储在缓存目录中。 然后，基于确定高速缓存行被缓存在较低级高速缓存中但不缓存在多个较高级别高速缓存中的任何一个中，高速缓存驱逐算法可以从高速缓存中选择用于驱逐的高速缓存行。

公开(公告)号：US20070168617A1

公开(公告)日：2007-07-19

申请号：US11335765

申请日：2006-01-19

Applicant: John Borkenhagen ,  Brian Vanderpool

Inventor： John Borkenhagen ,  Brian Vanderpool

IPC: G06F13/00 ,  G06F13/28

CPC classification number: G06F12/128 ,  G06F12/0897

Abstract: A computer system having patrol snoop sequencer that sequences through addresses of cache lines held in a higher level cache, making snoop reads using those addresses to a lower level cache. If a particular cache line held in the higher level cache is not held in the lower level cache, the particular cache line is identified as an eviction candidate in the higher level cache when a new cache line must be loaded into the higher level cache.

Abstract translation: 具有巡逻窥探音序器的计算机系统，其通过保持在较高级别高速缓存中的高速缓存行的地址进行排序，使得使用这些地址进行窥探读取到较低级别的高速缓存。 如果保持在较高级别高速缓存中的特定高速缓存行不被保持在较低级高速缓存中，则当新的高速缓存行必须被加载到更高级高速缓存中时，特定高速缓存行被标识为较高级高速缓存中的逐出候选。

公开(公告)号：US20060129726A1

公开(公告)日：2006-06-15

申请号：US11008813

申请日：2004-12-09

Applicant: Wayne Barrett ,  Brian Vanderpool

Inventor： Wayne Barrett ,  Brian Vanderpool

IPC: G06F13/00

CPC classification number: G06F13/1663

Abstract: In a first aspect, a first method is provided for processing commands on a bus. The first method includes the steps of (1) in a first phase of bus command processing, receiving a new command from a processor in a memory controller via the bus, wherein a command on the bus is processed in a plurality of sequential phases; (2) starting to perform memory controller tasks the results of which are required by a second phase of bus command processing; (3) before performing the second phase of bus command processing on the new command, determining whether there are any pending commands previously received in the memory controller that should complete before the second phase of processing is performed on the new command; and (4) if not, performing the second phase of processing on the new command without requiring the memory controller to insert a processing delay on the bus. Numerous other aspects are provided.

Abstract translation: 在第一方面，提供了一种用于在总线上处理命令的第一种方法。 第一种方法包括以下步骤：（1）在总线命令处理的第一阶段中，经由总线从存储器控制器中的处理器接收新的命令，其中总线上的命令以多个顺序相位被处理; （2）开始执行存储器控制器任务，其结果由总线命令处理的第二阶段所需; （3），在对所述新命令执行所述总线命令处理的第二阶段之前，确定在对所述新命令执行在所述第二阶段处理之前是否应该在所述存储器控制器中先前接收的任何未决命令; 和（4）否则，对新命令执行第二阶段处理，而不需要存储器控制器在总线上插入处理延迟。 提供了许多其他方面。

公开(公告)号：US20050021921A1

公开(公告)日：2005-01-27

申请号：US10625956

申请日：2003-07-24

Applicant: Herman Blackmon ,  Joseph Kirscht ,  James Marcella ,  Brian Vanderpool

Inventor： Herman Blackmon ,  Joseph Kirscht ,  James Marcella ,  Brian Vanderpool

IPC: G06F12/00 ,  G06F13/16

CPC classification number: G06F13/1631

Abstract: Methods and systems for re-ordering commands to access memory are disclosed. Embodiments may receive a first command to access a memory bank of the memory and determine a penalty associated with the first command based upon a conflict with an access to the memory bank. The penalty, in many embodiments, may be calculated so the penalty expires when the memory bank and a data bus associated with the memory bank are available to process the first command. Then, the first command is queued and dispatched to an available sequencer after the penalty expires. After the first command is serviced, unexpired penalties of subsequent commands may be updated to reflect a conflict with the first command. Further embodiments select a command to dispatch from the commands with expired penalties, based upon priorities associated with the commands such as the order in which the commands were received and the command types.

Abstract translation: 公开了将命令重新排序到访问存储器的方法和系统。 实施例可以接收访问存储器的存储体的第一命令，并且基于与访问存储体的冲突来确定与第一命令相关联的惩罚。 在许多实施例中，可以计算罚款，使得当与存储体相关联的存储体和数据总线可用于处理第一命令时，惩罚期满。 然后，第一个命令排队，并在惩罚到期后发送到可用的序列器。 在第一个命令被服务之后，可能会更新后续命令的未过期惩罚，以反映与第一个命令的冲突。 另外的实施例基于与诸如命令的接收顺序和命令类型的命令相关联的优先级，选择从具有过期惩罚的命令分派的命令。