中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.018 seconds)

    System and method for process control using in-situ thickness measurement
    2.
    发明申请
    System and method for process control using in-situ thickness measurement 审中-公开
    使用原位厚度测量的过程控制系统和方法

    公开(公告)号：US20060043071A1

    公开(公告)日：2006-03-02

    申请号：US10932194

    申请日：2004-09-02

    Applicant: Liang-Lun Lee ,  Chen-Shien Chen ,  Yai-Yei Huang ,  Chyi Chern

    Inventor： Liang-Lun Lee ,  Chen-Shien Chen ,  Yai-Yei Huang ,  Chyi Chern

    IPC: C03C15/00

    CPC classification number: H01L21/7684 ,  H01L22/12

    Abstract: A fabrication system. A plating tool generates a layer of conductive material on a substrate. A polishing tool uses a mechanical mechanism to remove the conductive material from the substrate. A metrology tool measures an electromagnetic signal induced in the conductive material using a non-destructive testing mechanism. A controller, coupled to the polishing and metrology tools, determines residue thickness and removal rate of the conductive material during the polishing process according to the measured electromagnetic signal, and adjusts process parameters for the plating and polishing tools accordingly.

    Abstract translation: 制造系统。 电镀工具在衬底上产生导电材料层。 抛光工具使用机械机构从衬底去除导电材料。 测量工具使用非破坏性测试机制来测量导电材料中感应的电磁信号。 耦合到抛光和计量工具的控制器根据测量的电磁信号确定抛光过程中导电材料的残余物厚度和去除速率，并相应地调整电镀和抛光工具的工艺参数。

    Construction of a film on a semiconductor wafer
    5.
    发明授权
    Construction of a film on a semiconductor wafer 失效
    在半导体晶片上构造膜

    公开(公告)号：US06251758B1

    公开(公告)日：2001-06-26

    申请号：US08810221

    申请日：1997-02-28

    Applicant: Chyi Chern ,  Michal Danek ,  Marvin Liao ,  Roderick C. Mosely ,  Karl Littau ,  Ivo Raaijmakers ,  David C. Smith

    Inventor： Chyi Chern ,  Michal Danek ,  Marvin Liao ,  Roderick C. Mosely ,  Karl Littau ,  Ivo Raaijmakers ,  David C. Smith

    IPC: H01L2128

    CPC classification number: H01L21/76864 ,  C23C16/34 ,  C23C16/45565 ,  C23C16/4581 ,  C23C16/4586 ,  C23C16/481 ,  C23C16/5096 ,  C23C16/56 ,  H01J37/32174 ,  H01J2237/2001 ,  H01J2237/336 ,  H01L21/28512 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862

    Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber. The rf signal means is coupled to the showerhead and the wafer support for providing a first rf signal to the showerhead and a second rf signal to the wafer support.

    Abstract translation: 放置在处理室中的晶片上的膜的构造可以通过以下步骤进行。 在晶片上沉积一层材料。 接下来，将材料层退火。 一旦退火完成，材料可能被氧化。 或者，一旦退火完成，材料可能暴露于硅气体。 沉积，退火和氧化或硅气体暴露都可以在相同的室中进行，而不需要从腔室中移除晶片，直到完成所有三个步骤。 用于进行这种原位结构的半导体晶片处理室可以包括处理室，喷头，晶片支架和射频信号装置。 淋浴头将气体供应到处理室中，而晶片支撑件在处理室中支撑晶片。 rf信号装置耦合到喷头和晶片支架，用于向喷头提供第一rf信号，并将第二rf信号耦合到晶片支架。

    High power, high luminous flux light emitting diode and method of making same
    6.
    发明申请
    High power, high luminous flux light emitting diode and method of making same 有权
    大功率，高光通量发光二极管及其制作方法

    公开(公告)号：US20050224823A1

    公开(公告)日：2005-10-13

    申请号：US11044714

    申请日：2005-01-28

    Applicant: Yongsheng Zhao ,  William So ,  Kevin Ma ,  Chyi Chern ,  Heng Liu ,  Eugene Ruddy

    Inventor： Yongsheng Zhao ,  William So ,  Kevin Ma ,  Chyi Chern ,  Heng Liu ,  Eugene Ruddy

    IPC: H01L29/18 ,  H01L33/08 ,  H01L33/38 ,  H01L33/46 ,  H01L33/00

    CPC classification number: H01L33/38 ,  H01L33/08 ,  H01L33/20 ,  H01L33/46

    Abstract: A high power, high luminous flux light emitting diode (LED) comprises a substrate, a light-emitting structure, a first electrode and a second electrode. The LED has a top surface layout design in which the first electrode has a number of legs extending in one direction, and the second electrode has a number of legs extending in the opposite direction. At least portions of the legs of the first electrode are interspersed with and spaced apart from portions of the legs of the second electrode. This provides a configuration that enhances current spreading along the length of the legs of both electrodes.

    Abstract translation: 高功率，高光通量发光二极管（LED）包括基板，发光结构，第一电极和第二电极。 LED具有顶表面布局设计，其中第一电极具有沿一个方向延伸的多个支脚，并且第二电极具有沿相反方向延伸的多个支脚。 第一电极的腿部的至少部分与第二电极的腿的部分分开并间隔开。 这提供了增强沿着两个电极的腿的长度的电流扩散的配置。

    Construction of a film on a semiconductor wafer
    7.
    发明授权
    Construction of a film on a semiconductor wafer 失效
    在半导体晶片上构造膜

    公开(公告)号：US06444036B2

    公开(公告)日：2002-09-03

    申请号：US09737681

    申请日：2000-12-15

    Applicant: Chyi Chern ,  Michal Danek ,  Marvin Liao ,  Roderick C. Mosely ,  Karl Littau ,  Ivo Raaijmakers ,  David C. Smith

    Inventor： Chyi Chern ,  Michal Danek ,  Marvin Liao ,  Roderick C. Mosely ,  Karl Littau ,  Ivo Raaijmakers ,  David C. Smith

    IPC: B05C1100

    CPC classification number: H01L21/76864 ,  C23C16/34 ,  C23C16/45565 ,  C23C16/4581 ,  C23C16/4586 ,  C23C16/481 ,  C23C16/5096 ,  C23C16/56 ,  H01J37/32174 ,  H01J2237/2001 ,  H01J2237/336 ,  H01L21/28512 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76862

    Abstract: The construction of a film on a wafer, which is placed in a processing chamber, may be carried out through the following steps. A layer of material is deposited on the wafer. Next, the layer of material is annealed. Once the annealing is completed, the material may be oxidized. Alternatively, the material may be exposed to a silicon gas once the annealing is completed. The deposition, annealing, and either oxidation or silicon gas exposure may all be carried out in the same chamber, without need for removing the wafer from the chamber until all three steps are completed. A semiconductor wafer processing chamber for carrying out such an in-situ construction may include a processing chamber, a showerhead, a wafer support and a rf signal means. The showerhead supplies gases into the processing chamber, while the wafer support supports a wafer in the processing chamber. The rf signal means is coupled to the showerhead and the wafer support for providing a first rf signal to the showerhead and a second rf signal to the wafer support.

    Abstract translation: 放置在处理室中的晶片上的膜的构造可以通过以下步骤进行。 在晶片上沉积一层材料。 接下来，将材料层退火。 一旦退火完成，材料可能被氧化。 或者，一旦退火完成，材料可能暴露于硅气体。 沉积，退火和氧化或硅气体暴露都可以在相同的室中进行，而不需要从腔室中移除晶片，直到完成所有三个步骤。 用于进行这种原位结构的半导体晶片处理室可以包括处理室，喷头，晶片支架和射频信号装置。 淋浴头将气体供应到处理室中，而晶片支撑件在处理室中支撑晶片。 rf信号装置耦合到喷头和晶片支架，用于向喷头提供第一rf信号，并将第二rf信号耦合到晶片支架。

    Interconnect structure for semiconductor devices
    9.
    发明申请
    Interconnect structure for semiconductor devices 有权
    半导体器件的互连结构

    公开(公告)号：US20070034517A1

    公开(公告)日：2007-02-15

    申请号：US11197009

    申请日：2005-08-04

    Applicant: Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin ,  Chyi Chern

    Inventor： Jung-Chih Tsao ,  Kei-Wei Chen ,  Yu-Ku Lin ,  Chyi Chern

    IPC: B05D5/12 ,  C25D5/02

    CPC classification number: C25D5/10 ,  C25D5/18 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76847 ,  H01L21/76877

    Abstract: An interconnect structure for a semiconductor device and its method of manufacture is described. The interconnect structure comprises a multi-layer structure having one or more stress-relief layers. In an embodiment, stress-relief layers are positioned between layers of electroplated copper or other conductive material. The stress-relief layer counteracts stress induced by the conductive material and helps prevent or reduce a pull-back void. For an interconnect structure using electroplated copper, the stress-relief layer may be formed by temporarily reducing the electroplating current, thereby causing a thin film of copper having a larger grain size to be formed between other layers of copper. The larger grain size typically exhibits more of a compressive stress than copper with a smaller grain size. The stress relief layer may also be formed of other materials, such as SIP-Cu, Ta, SiC, or the like.

    Abstract translation: 描述了半导体器件的互连结构及其制造方法。 互连结构包括具有一个或多个应力消除层的多层结构。 在一个实施例中，应力消除层位于电镀铜或其它导电材料的层之间。 应力消除层抵消由导电材料引起的应力，并有助于防止或减少拉回空隙。 对于使用电镀铜的互连结构，可以通过暂时减少电镀电流来形成应力消除层，从而在其它铜层之间形成具有较大晶粒尺寸的铜的薄膜。 较大的晶粒尺寸通常表现出比具有较小晶粒尺寸的铜更多的压缩应力。 应力消除层也可以由其它材料形成，例如SIP-Cu，Ta，SiC等。

Patent Agency Ranking