公开(公告)号：US07948772B2

公开(公告)日：2011-05-24

申请号：US12371794

申请日：2009-02-16

Applicant: Yueh-Ming Tung ,  Kuo-Yang Sun ,  Chia-Ming Yang ,  Chung-Lun Lee ,  Jin-Chun Wen ,  Yuan-Wei Liu ,  Wei-Mao Hung

Inventor： Yueh-Ming Tung ,  Kuo-Yang Sun ,  Chia-Ming Yang ,  Chung-Lun Lee ,  Jin-Chun Wen ,  Yuan-Wei Liu ,  Wei-Mao Hung

IPC: H05K9/00

CPC classification number: H05K1/0259 ,  H05K2201/09336 ,  H05K2201/09354 ,  H05K2201/10159 ,  Y10T29/4913

Abstract: A memory card with electrostatic discharge (ESD) protection and a manufacturing method thereof are provided. The memory card includes a circuit board, a set of contacts, at least one chip and an ESD protection path. The signal paths of the board is not exposed at the edge of the circuit board. The ESD protection path for transmitting ESD current is disposed on the circuit board. Furthermore, a part of the ESD protection path extends to the edge of the circuit board.

Abstract translation: 提供一种具有静电放电（ESD）保护的存储卡及其制造方法。 存储卡包括电路板，一组触点，至少一个芯片和ESD保护路径。 板的信号路径不暴露在电路板的边缘。 用于传输ESD电流的ESD保护路径设置在电路板上。 此外，ESD保护路径的一部分延伸到电路板的边缘。

公开(公告)号：US20060001134A1

公开(公告)日：2006-01-05

申请号：US10711794

申请日：2004-10-06

Applicant: Kuo-Yang Sun ,  Chia-Ming Yang

Inventor： Kuo-Yang Sun ,  Chia-Ming Yang

IPC: H01L23/48

CPC classification number: H01L24/16 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package structure includes a lead frame having a plurality of leads, each of which includes a first recession, at least a first device, and a plurality of solder joints respectively positioned in the first recessions for connecting the first device to the lead frame.

Abstract translation: 封装结构包括具有多个引线的引线框架，每个引线包括第一凹陷，至少第一器件和分别位于第一凹部中的多个焊点，用于将第一器件连接到引线框架。

公开(公告)号：US07394147B2

公开(公告)日：2008-07-01

申请号：US11053660

申请日：2005-02-09

Applicant: Kuo Yang Sun ,  Chia Ming Yang ,  Hung Yuan Lu ,  Wei Chin Tsai ,  Yi Cheng Lin

Inventor： Kuo Yang Sun ,  Chia Ming Yang ,  Hung Yuan Lu ,  Wei Chin Tsai ,  Yi Cheng Lin

IPC: H01L23/495

CPC classification number: H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L25/0652 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/83139 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes a substrate, a first chip, a nonconductive adhesive, a second chip and a plurality of supporting balls. The first chip has an upper surface and a lower surface opposite to the upper surface, and the lower surface is mounted on the substrate. The nonconductive adhesive is disposed on the upper surface of the first chip. The second chip has an upper surface and a lower surface opposite to the upper surface, wherein the lower surface is mounted on the upper surface of the first chip by means of the nonconductive adhesive, and the adherent area between the nonconductive adhesive and the second chip is larger than 90% of the area of the lower surface of the second chip. The supporting balls are disposed in the nonconductive adhesive for supporting the second chip.

Abstract translation: 半导体封装包括衬底，第一芯片，非导电粘合剂，第二芯片和多个支撑球。 第一芯片具有与上表面相对的上表面和下表面，并且下表面安装在基板上。 非导电粘合剂设置在第一芯片的上表面上。 第二芯片具有与上表面相对的上表面和下表面，其中下表面通过非导电粘合剂安装在第一芯片的上表面上，并且非导电粘合剂和第二芯片之间的粘合区域 大于第二芯片的下表面面积的90％。 支撑球设置在用于支撑第二芯片的非导电粘合剂中。

公开(公告)号：US20060097129A1

公开(公告)日：2006-05-11

申请号：US10984454

申请日：2004-11-10

Applicant: Kuo-Yang Sun ,  Chia-Ming Yang ,  Li-Ju Huang ,  Juin-Lin Lee ,  Yi-Jeng Lin

Inventor： Kuo-Yang Sun ,  Chia-Ming Yang ,  Li-Ju Huang ,  Juin-Lin Lee ,  Yi-Jeng Lin

IPC: H01L27/00 ,  H01J3/14

CPC classification number: H04N5/2257 ,  H01L27/14618 ,  H01L31/0203 ,  H01L31/0232 ,  H01L2224/48091 ,  H04N5/2253 ,  H04N5/2254 ,  H01L2924/00014

Abstract: A lens module structure includes an image sensing chip disposed on the first side of a substrate and electrically coupled to the substrate through wires. A memory chip and a control chip are soldered onto a second surface of the substrate, and a solderable output unit terminal is provided on one side of the second surface of the substrate for connecting to other electronic components. A lens pedestal is fastened onto the first surface of the substrate such that the image sensing chip is encapsulated within the lens pedestal, and an optical lens is provided within the lens pedestal and corresponding to the image sensing chip. In such way, the assembled components of the lens are decreased and the chips thereof are designed in a modular mode such that the overall volume of the lens is reduced and the surface mounting technologies can be omitted.

Abstract translation: 透镜模块结构包括设置在基板的第一侧上的图像感测芯片，并通过导线电耦合到基板。 存储器芯片和控制芯片焊接到基板的第二表面上，并且可焊接的输出单元端子设置在基板的第二表面的一侧，用于连接到其他电子部件。 将透镜基座固定在基板的第一表面上，使得图像感测芯片被封装在透镜基座内，并且在透镜基座内并且对应于图像感测芯片设置光学透镜。 以这种方式，透镜的组装部件减小，并且其芯片被设计成模块化模式，使得透镜的总体积减小，并且可以省略表面安装技术。

公开(公告)号：US20090154040A1

公开(公告)日：2009-06-18

申请号：US12371794

申请日：2009-02-16

Applicant: Yueh-Ming Tung ,  Kuo-Yang Sun ,  Chia-Ming Yang ,  Chung-Lun Lee ,  Jin-Chun Wen ,  Yuan-Wei Liu ,  Wei-Mao Hung

Inventor： Yueh-Ming Tung ,  Kuo-Yang Sun ,  Chia-Ming Yang ,  Chung-Lun Lee ,  Jin-Chun Wen ,  Yuan-Wei Liu ,  Wei-Mao Hung

IPC: H02H9/04 ,  H05K3/30

CPC classification number: H05K1/0259 ,  H05K2201/09336 ,  H05K2201/09354 ,  H05K2201/10159 ,  Y10T29/4913

Abstract: A memory card with electrostatic discharge (ESD) protection and a manufacturing method thereof are provided. The memory card includes a circuit board, a set of contacts, at least one chip and an ESD protection path. The signal paths of the board is not exposed at the edge of the circuit board. The ESD protection path for transmitting ESD current is disposed on the circuit board. Furthermore, a part of the ESD protection path extends to the edge of the circuit board.

Abstract translation: 提供一种具有静电放电（ESD）保护的存储卡及其制造方法。 存储卡包括电路板，一组触点，至少一个芯片和ESD保护路径。 板的信号路径不暴露在电路板的边缘。 用于传输ESD电流的ESD保护路径设置在电路板上。 此外，ESD保护路径的一部分延伸到电路板的边缘。

公开(公告)号：US20080113472A1

公开(公告)日：2008-05-15

申请号：US11979792

申请日：2007-11-08

Applicant: Yueh Ming Tung ,  Kuo Yang Sun ,  Chia Ming Yang ,  Hung Tai Mai ,  Hui Chi Liu

Inventor： Yueh Ming Tung ,  Kuo Yang Sun ,  Chia Ming Yang ,  Hung Tai Mai ,  Hui Chi Liu

IPC: H01L21/58 ,  B32B5/16 ,  B32B7/12

CPC classification number: H01L24/29 ,  H01L21/6835 ,  H01L24/27 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/05624 ,  H01L2224/274 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83139 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19103 ,  Y10T428/25 ,  Y10T428/28 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A film includes a removable base material, a resin layer and a plurality of arc elastomers. The resin layer is a partially-cured resin which is in a half-melting state with viscosity at a temperature higher than a first temperature and in a solid state without viscosity at a temperature lower than a second temperature, and the resin layer in a solid state is adhered on the base material. The arc elastomers are disposed inside the resin layer. The present invention further provides a chip packaging process using the film.

Abstract translation: 膜包括可移除的基底材料，树脂层和多个弧形弹性体。 树脂层是部分固化的树脂，其处于比第一温度高的粘度的半熔融状态，并且在低于第二温度的温度下没有粘度的固态，并且固体中的树脂层 状态粘附在基材上。 电弧弹性体设置在树脂层的内部。 本发明进一步提供使用该膜的芯片封装方法。

公开(公告)号：US20080007932A1

公开(公告)日：2008-01-10

申请号：US11531000

申请日：2006-09-12

Applicant: Yueh-Ming Tung ,  Kuo-Yang Sun ,  Chia-Ming Yang ,  Chung-Lun Lee ,  Jin-Chun Wen ,  Yuan-Wei Liu ,  Wei-Mao Hung

Inventor： Yueh-Ming Tung ,  Kuo-Yang Sun ,  Chia-Ming Yang ,  Chung-Lun Lee ,  Jin-Chun Wen ,  Yuan-Wei Liu ,  Wei-Mao Hung

IPC: H05K9/00

CPC classification number: H05K1/0259 ,  G06K19/07 ,  G06K19/07732 ,  H05K2201/09336 ,  H05K2201/09354 ,  H05K2201/10159

Abstract: A memory card with electrostatic discharge (ESD) protection is provided. The memory card includes a board, a set of contacts, at least one chip and an ESD protection path. The board having a signal path not electrically connected to the edge of the board. The ESD protection path for transmitting ESD current is disposed on the board. Furthermore, a part of the ESD protection path extends to the edge of the board.

Abstract translation: 提供了具有静电放电（ESD）保护的存储卡。 存储卡包括板，一组触点，至少一个芯片和ESD保护路径。 该电路板具有不电连接到电路板边缘的信号路径。 用于传输ESD电流的ESD保护路径配置

公开(公告)号：US20070205493A1

公开(公告)日：2007-09-06

申请号：US11450996

申请日：2006-06-12

Applicant: Yueh-Ming Tung ,  Kuo-Yang Sun ,  Chia-Ming Yang ,  Hung-Tai Mai ,  Hui-Ying Hsu

Inventor： Yueh-Ming Tung ,  Kuo-Yang Sun ,  Chia-Ming Yang ,  Hung-Tai Mai ,  Hui-Ying Hsu

IPC: H01L23/495

CPC classification number: H01L23/49582 ,  H01L21/568 ,  H01L24/28 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package structure is disclosed. The structure includes a lead frame, a semiconductor chip, a plurality of metallic conducting wires, an encapsulation, a barrier layer and a pure tin layer, herein the lead frame has at least one die pad, a plurality of inner leads and outer leads. The semiconductor chip is disposed on the die pad. The metallic conducting wires electrically connect the semiconductor chip and the inner leads. The encapsulation packages of the semiconductor chip, the die pad, the metallic conducting wires and the inner leads. The barrier layer covers each of the outer leads to prevent an inter-metallic compound produced by the outer leads and pure tin. The pure tin layer covers the barrier layer to increase the solder wettability for the outer leads. Besides, a method for manufacturing the semiconductor package structure is disclosed.

Abstract translation: 公开了半导体封装结构。 该结构包括引线框架，半导体芯片，多个金属导线，封装，阻挡层和纯锡层，这里引线框架具有至少一个管芯焊盘，多个内部引线和外部引线。 半导体芯片设置在芯片焊盘上。 金属导线将半导体芯片和内部引线电连接。 半导体芯片，芯片焊盘，金属导线和内部引线的封装封装。 阻挡层覆盖每个外引线，以防止由外引线和纯锡产生的金属间化合物。 纯锡层覆盖阻挡层以增加外引线的焊料润湿性。 此外，公开了一种用于制造半导体封装结构的方法。

公开(公告)号：US07115978B2

公开(公告)日：2006-10-03

申请号：US10711794

申请日：2004-10-06

Applicant: Kuo-Yang Sun ,  Chia-Ming Yang

Inventor： Kuo-Yang Sun ,  Chia-Ming Yang

IPC: H01L23/495 ,  H01L23/52

CPC classification number: H01L24/16 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/13099 ,  H01L2224/16245 ,  H01L2224/48247 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package structure includes a lead frame having a plurality of leads, each of which includes a first recession, at least a first device, and a plurality of solder joints respectively positioned in the first recessions for connecting the first device to the lead frame.

Abstract translation: 封装结构包括具有多个引线的引线框架，每个引线包括第一凹陷，至少第一器件和分别位于第一凹部中的多个焊点，用于将第一器件连接到引线框架。