公开(公告)号：US08283570B2

公开(公告)日：2012-10-09

申请号：US12674081

申请日：2008-11-11

Applicant: Yoshihiro Tomura ,  Shigeru Kondou ,  Teppei Iwase

Inventor： Yoshihiro Tomura ,  Shigeru Kondou ,  Teppei Iwase

IPC: H05K1/00

CPC classification number: H05K1/0271 ,  H01L21/563 ,  H01L23/3735 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/75314 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/3494 ,  H05K3/4626 ,  H05K2201/062 ,  H05K2201/09136 ,  H05K2201/10674 ,  H05K2203/0195 ,  H05K2203/0278 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor assembly includes a multilayer wiring board including at least three insulating layers, first, second and third insulating layers and a semiconductor device attached to one principal surface of the first insulating layer. The first, second and third insulating layers are stacked in this order. The multilayer wiring board further includes a heat-insulating member made of a material having a lower thermal conductivity than the insulating layers. The heat-insulating member is disposed between the first and second insulating layers or next to the first insulating layer at a side opposite to the one principal surface.

Abstract translation: 半导体组件包括多层布线板，其包括至少三个绝缘层，第一绝缘层，第二绝缘层和第三绝缘层，以及附接到第一绝缘层的一个主表面的半导体器件。 第一，第二和第三绝缘层按此顺序堆叠。 多层布线基板还包括由比绝缘层低的热导率的材料制成的绝热构件。 隔热构件设置在第一绝缘层和第二绝缘层之间或与第一绝缘层相邻的一个主表面相对的一侧。

公开(公告)号：US08264079B2

公开(公告)日：2012-09-11

申请号：US12666860

申请日：2008-06-26

Applicant: Teppei Iwase ,  Yoshihiro Tomura ,  Kazuhiro Nobori ,  Yuichiro Yamada ,  Kentaro Kumazawa

Inventor： Teppei Iwase ,  Yoshihiro Tomura ,  Kazuhiro Nobori ,  Yuichiro Yamada ,  Kentaro Kumazawa

IPC: H01L23/48

CPC classification number: H01L24/75 ,  B30B5/02 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75252 ,  H01L2224/75303 ,  H01L2224/75315 ,  H01L2224/75756 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. Entire side faces at corner portions of the semiconductor chip are covered with the seal-bonding resin. Therefore, loads generated at the corner portions due to board flexures for thermal expansion and contraction differences among the individual members caused by heating and cooling during mounting as well as for mechanical loads after mounting so that internal breakdown of the semiconductor chip can be avoided.

Abstract translation: 当形成在半导体芯片的焊盘上的凸起和具有粘附在其表面上的片状密封粘合树脂的板彼此面对地设置时，用工具将凸块和板彼此挤压，从而形成半导体芯片 其中密封粘合树脂填充在半导体芯片和板之间，并且其中半导体芯片的焊盘和板的电极分别经由凸块相互连接。 半导体芯片的角部的整个侧面被密封接合树脂覆盖。 因此，由于板弯曲而在安装期间由加热和冷却引起的各个部件之间的热膨胀和收缩差异的板弯曲产生的负载以及安装之后的机械负载，从而可以避免半导体芯片的内部击穿。

公开(公告)号：US20110279996A1

公开(公告)日：2011-11-17

申请号：US12674081

申请日：2008-11-11

Applicant: Yoshihiro Tomura ,  Shigeru Kondou ,  Teppei Iwase

Inventor： Yoshihiro Tomura ,  Shigeru Kondou ,  Teppei Iwase

IPC: H05K7/00 ,  H05K1/00

CPC classification number: H05K1/0271 ,  H01L21/563 ,  H01L23/3735 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/75252 ,  H01L2224/75314 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/83192 ,  H01L2224/9211 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/3494 ,  H05K3/4626 ,  H05K2201/062 ,  H05K2201/09136 ,  H05K2201/10674 ,  H05K2203/0195 ,  H05K2203/0278 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A multilayer wiring board is inhibited from being warped when flip-chip bonding a semiconductor device to the multilayer wiring board, thereby increasing the reliability of connecting the semiconductor assembly to a motherboard.A heat-insulating layer 10 is provided between a core board 1 and a flip-chip bonding-side insulating layer 3 in a multilayer wiring board MB1, thereby preventing thermal conduction from a heat tool, so that the amounts of thermal expansion of the core board 1 and an insulating layer 4 are minimized, resulting in reduced warpage of the multilayer wiring board MB1.

Abstract translation: 当将半导体器件倒装成多层布线板时，多层布线板被阻止翘曲，从而提高将半导体组件连接到母板上的可靠性。 在多层布线板MB1中的芯板1和倒装芯片接合侧绝缘层3之间设置隔热层10，从而防止热工具的热传导，使得芯的热膨胀量 板1和绝缘层4最小化，导致多层布线板MB1的翘曲减小。

公开(公告)号：US20100181667A1

公开(公告)日：2010-07-22

申请号：US12666860

申请日：2008-06-26

Applicant: Teppei Iwase ,  Yoshihiro Tomura ,  Kazuhiro Nobori ,  Yuichiro Yamada ,  Kentaro Kumazawa

Inventor： Teppei Iwase ,  Yoshihiro Tomura ,  Kazuhiro Nobori ,  Yuichiro Yamada ,  Kentaro Kumazawa

IPC: H01L23/28 ,  H01L21/56 ,  B32B37/10

CPC classification number: H01L24/75 ,  B30B5/02 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75252 ,  H01L2224/75303 ,  H01L2224/75315 ,  H01L2224/75756 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding use resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding use resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. In the semiconductor chip mounted structure formed in this way, entire side faces at the corner portions of the semiconductor chip are covered with the seal-bonding use resin. As a result, loads generated at corner portions of the semiconductor chip due to board flexures for thermal expansion differences and thermal contraction differences among the individual members caused by heating process and cooling process in mounting operation as well as for mechanical loads after the mounting operation so that internal breakdown of the semiconductor chip can be avoided.

Abstract translation: 当在半导体芯片的焊盘上形成的凸起和具有粘附在其表面上的片状密封用树脂的基板面对面地设置时，用工具将凸块和板彼此挤压，从而形成半导体 分别在半导体芯片和板之间填充密封用树脂并且其中半导体芯片的焊盘和板的电极通过凸块相互连接的芯片安装结构。 在以这种方式形成的半导体芯片安装结构中，用密封接合用树脂覆盖半导体芯片的角部的整个侧面。 结果，由于板弯曲导致的半导体芯片的角部处的负载产生的热膨胀差异和各个部件之间的热收缩差异由安装操作中的加热处理和冷却过程以及安装操作之后的机械负载引起。 可以避免半导体芯片的内部故障。

公开(公告)号：US20100127382A1

公开(公告)日：2010-05-27

申请号：US12566165

申请日：2009-09-24

Applicant: Toshitaka AKAHOSHI ,  Teppei IWASE ,  Yoshiaki TAKEOKA

Inventor： Toshitaka AKAHOSHI ,  Teppei IWASE ,  Yoshiaki TAKEOKA

IPC: H01L23/48 ,  H01L23/482

CPC classification number: H01L23/147 ,  H01L23/13 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L2224/0401 ,  H01L2224/0612 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15787 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A semiconductor device includes: a semiconductor carrier with a top surface on which a plurality of electrodes are disposed; and a semiconductor element electrically connected through a plurality of bump electrodes to the plurality of associated electrodes. The plurality of electrodes are substantially uniformly spaced.

Abstract translation: 半导体器件包括：具有顶表面的半导体载体，多个电极设置在其上; 以及通过多个凸起电极电连接到所述多个相关电极的半导体元件。 多个电极基本上均匀间隔开。

公开(公告)号：US20120298310A1

公开(公告)日：2012-11-29

申请号：US13567112

申请日：2012-08-06

Applicant: Teppei IWASE ,  Yoshihiro Tomura ,  Kazuhiro Nobori ,  Yuichiro Yamada ,  Kentaro Kumazawa

Inventor： Teppei IWASE ,  Yoshihiro Tomura ,  Kazuhiro Nobori ,  Yuichiro Yamada ,  Kentaro Kumazawa

IPC: B30B9/00

CPC classification number: H01L24/75 ,  B30B5/02 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3121 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75252 ,  H01L2224/75303 ,  H01L2224/75315 ,  H01L2224/75756 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/18161 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. Entire side faces at corner portions of the semiconductor chip are covered with the seal-bonding resin. Therefore, loads generated at the corner portions due to board flexures for thermal expansion and contraction differences among the individual members caused by heating and cooling during mounting as well as for mechanical loads after mounting so that internal breakdown of the semiconductor chip can be avoided.

Abstract translation: 当形成在半导体芯片的焊盘上的凸起和具有粘附在其表面上的片状密封粘合树脂的板彼此面对地设置时，用工具将凸块和板彼此挤压，从而形成半导体芯片 其中密封粘合树脂填充在半导体芯片和板之间，并且其中半导体芯片的焊盘和板的电极分别经由凸块相互连接。 半导体芯片的角部的整个侧面被密封接合树脂覆盖。 因此，由于板弯曲而在安装期间由加热和冷却引起的各个部件之间的热膨胀和收缩差异的板弯曲产生的负载以及安装之后的机械负载，从而可以避免半导体芯片的内部击穿。

公开(公告)号：US20100265683A1

公开(公告)日：2010-10-21

申请号：US12427056

申请日：2009-04-21

Applicant: Teppei IWASE ,  Kazuhiro NOBORI ,  Yoshihiro TOMURA ,  Koujiro NAKAMURA ,  Kentaro Kumazawa

Inventor： Teppei IWASE ,  Kazuhiro NOBORI ,  Yoshihiro TOMURA ,  Koujiro NAKAMURA ,  Kentaro Kumazawa

IPC: H05K7/02

CPC classification number: H05K1/181 ,  H05K3/284 ,  H05K3/305 ,  H05K2201/0133 ,  H05K2201/09036 ,  H05K2201/09909 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/611

Abstract: The present invention provides a semiconductor device of a double-side mounting structure including a circuit board and a plurality of semiconductor chips arranged and joined together on the opposite surfaces of the circuit board, wherein in an area in which the semiconductor chip 31 mounted on the top surface of the circuit board 2 overlaps with the semiconductor chip 32 mounted on the bottom surface of the circuit board 2, a recess portion (or a protruding portion 22) is formed in the surfaces of the circuit board 2.

Abstract translation: 本发明提供了一种双面安装结构的半导体器件，其包括在电路板的相对表面上布置和接合在一起的电路板和多个半导体芯片，其中在安装在电路板上的半导体芯片31的区域中 电路板2的上表面与安装在电路基板2的底面上的半导体芯片32重叠，在电路基板2的表面形成有凹部（或突出部22）。

公开(公告)号：US20100032832A1

公开(公告)日：2010-02-11

申请号：US12531819

申请日：2008-05-09

Applicant: Yoshihiro Tomura ,  Kazuhiro Nobori ,  Yuichiro Yamada ,  Kentaro Kumazawa ,  Teppei Iwase

Inventor： Yoshihiro Tomura ,  Kazuhiro Nobori ,  Yuichiro Yamada ,  Kentaro Kumazawa ,  Teppei Iwase

IPC: H01L23/488

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05076 ,  H01L2224/05554 ,  H01L2224/05576 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In this semiconductor chip 3, a table electrode 13 is interposed between a bump electrode 14 and an electrode pad 6. The table electrode 13 is formed by forming a plurality of cores 15 having a smaller Young's modulus than the bump electrode 14, on the electrode pad 6, and then covering the surfaces of the cores 15 with a conductive electrode 16. When the semiconductor chip 3 is flip-chip mounted, the bump electrode 14 is plastically deformed and the table electrode 13 is elastically deformed appropriately, thereby obtaining a good conductive state.

Abstract translation: 在该半导体芯片3中，台面电极13插入在凸块电极14和电极焊盘6之间。台电极13通过在电极上形成具有比突起电极14更小的杨氏模量的多个芯15而形成 垫6，然后用导电电极16覆盖芯15的表面。当半导体芯片3倒装芯片安装时，凸起电极14塑性变形，并且台面电极13被适当地弹性变形，从而获得良好的 导电状态。

公开(公告)号：US08050049B2

公开(公告)日：2011-11-01

申请号：US12427056

申请日：2009-04-21

Applicant: Teppei Iwase ,  Kazuhiro Nobori ,  Yoshihiro Tomura ,  Koujiro Nakamura ,  Kentaro Kumazawa

Inventor： Teppei Iwase ,  Kazuhiro Nobori ,  Yoshihiro Tomura ,  Koujiro Nakamura ,  Kentaro Kumazawa

IPC: H05K7/00

CPC classification number: H05K1/181 ,  H05K3/284 ,  H05K3/305 ,  H05K2201/0133 ,  H05K2201/09036 ,  H05K2201/09909 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/611

Abstract: The present invention provides a semiconductor device of a double-side mounting structure including a circuit board and a plurality of semiconductor chips arranged and joined together on the opposite surfaces of the circuit board, wherein in an area in which the semiconductor chip 31 mounted on the top surface of the circuit board 2 overlaps with the semiconductor chip 32 mounted on the bottom surface of the circuit board 2, a recess portion 21 (or a protruding portion 22) is formed in the surfaces of the circuit board 2.

Abstract translation: 本发明提供了一种双面安装结构的半导体器件，其包括在电路板的相对表面上布置和接合在一起的电路板和多个半导体芯片，其中在安装在电路板上的半导体芯片31的区域中 电路板2的顶面与安装在电路基板2的底面的半导体芯片32重叠，在电路基板2的表面形成有凹部21（或突出部22）。

公开(公告)号：US07994638B2

公开(公告)日：2011-08-09

申请号：US12531819

申请日：2008-05-09

Applicant: Yoshihiro Tomura ,  Kazuhiro Nobori ,  Yuichiro Yamada ,  Kentaro Kumazawa ,  Teppei Iwase

Inventor： Yoshihiro Tomura ,  Kazuhiro Nobori ,  Yuichiro Yamada ,  Kentaro Kumazawa ,  Teppei Iwase

IPC: H01L23/488

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02125 ,  H01L2224/0401 ,  H01L2224/05076 ,  H01L2224/05554 ,  H01L2224/05576 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In this semiconductor chip 3, a table electrode 13 is interposed between a bump electrode 14 and an electrode pad 6. The table electrode 13 is formed by forming a plurality of cores 15 having a smaller Young's modulus than the bump electrode 14, on the electrode pad 6, and then covering the surfaces of the cores 15 with a conductive electrode 16. When the semiconductor chip 3 is flip-chip mounted, the bump electrode 14 is plastically deformed and the table electrode 13 is elastically deformed appropriately, thereby obtaining a good conductive state.

Abstract translation: 在该半导体芯片3中，台面电极13插入在凸块电极14和电极焊盘6之间。台电极13通过在电极上形成具有比突起电极14更小的杨氏模量的多个芯15而形成 垫6，然后用导电电极16覆盖芯15的表面。当半导体芯片3倒装芯片安装时，凸起电极14塑性变形，并且台面电极13被适当地弹性变形，从而获得良好的 导电状态。