公开(公告)号：US08575011B2

公开(公告)日：2013-11-05

申请号：US12061403

申请日：2008-04-02

Applicant: Daniel-Camille Bensahel ,  Yves Morand

Inventor： Daniel-Camille Bensahel ,  Yves Morand

IPC: H01L21/50

CPC classification number: H01L21/22 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/36 ,  H01L29/66659

Abstract: A semiconductive device is fabricated by forming, within a semiconductive substrate, at least one continuous region formed of a material having a non-uniform composition in a direction substantially perpendicular to the thickness of the substrate.

Abstract translation: 半导体器件通过在半导体衬底内形成至少一个由具有基本上垂直于衬底厚度的方向上具有不均匀组成的材料形成的连续区域来制造。

公开(公告)号：US20130252412A1

公开(公告)日：2013-09-26

申请号：US13811792

申请日：2011-07-22

Applicant: Thierry Poiroux ,  Sébastien Barnola ,  Yves Morand

Inventor： Thierry Poiroux ,  Sébastien Barnola ,  Yves Morand

IPC: H01L21/8234

CPC classification number: H01L21/823468 ,  H01L21/76897 ,  H01L21/823456 ,  H01L21/823475 ,  H01L27/11 ,  H01L27/11521

Abstract: A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones.

Abstract translation: 一种用于在基板表面上制造集成电路的方法，所述方法包括：在所述基板的表面上产生包括有源区和绝缘区的第一层; 在所述第一层的表面上产生栅极区域，所述栅极区域各自被绝缘间隔物包围; 产生源极/漏极; 在所述绝缘间隔物之间​​产生电介质层，所述电介质层具有与所述栅极区的上表面的上表面水平; 部分地蚀刻每个栅极区，以便降低每个栅极区的第一部分的上表面; 以及在栅极区域的第一部分上沉积绝缘介电层。

公开(公告)号：US08486514B2

公开(公告)日：2013-07-16

申请号：US12715738

申请日：2010-03-02

Applicant: Stéfan Landis ,  Yves Morand

Inventor： Stéfan Landis ,  Yves Morand

IPC: B32B3/28 ,  B32B3/30

CPC classification number: G03F7/0002 ,  B29C33/42 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/0017 ,  Y10T428/24479 ,  Y10T428/2457 ,  Y10T428/24744

Abstract: A nano-imprint device including at least: a substrate, having a surface, on the substrate, a plurality of nano-trenches parallel two by two, each nano-trench extending in a longitudinal direction and being delimited laterally by side walls, the nano-trenches and the side walls being directed substantially perpendicular to the surface of the substrate, each nano-trench comprising a bottom surface with at least one first and one second level in a direction perpendicular to the substrate, respectively of depth h1 and h2>h1, measured relative to the top of the side walls, and the bottom surfaces of the nano-trenches, of the least deep level (h1) being in a first type of material, the side walls being in a second type of material.

Abstract translation: 一种纳米压印装置，其至少包括：在所述基板上具有平行两个的多个纳米沟槽的表面的基板，每个纳米沟槽在纵向方向上延伸并由侧壁横向限定，所述纳米沟槽 三角形并且所述侧壁基本上垂直于所述衬底的表面定向，每个纳米沟槽包括底面，所述底表面在垂直于所述衬底的方向上具有至少一个第一和第二水平面，所述方向分别具有深度h1和h2> h1 （h1）处于第一类型的材料中，相对于侧壁的顶部和纳米沟槽的底表面测量的最小深度（h1）的底表面是第二类型的材料。

公开(公告)号：US20120115311A1

公开(公告)日：2012-05-10

申请号：US13293652

申请日：2011-11-10

Applicant: Sébastien DESPLOBAIN ,  Frederic-Xavier GAILLARD ,  Yves MORAND ,  Fabrice NEMOUCHI

Inventor： Sébastien DESPLOBAIN ,  Frederic-Xavier GAILLARD ,  Yves MORAND ,  Fabrice NEMOUCHI

IPC: H01L21/30

CPC classification number: H01L21/306 ,  B81C1/0038 ,  B81C2201/0109 ,  B81C2201/0115

Abstract: The method for forming a multilayer structure on a substrate comprises providing a stack successively comprising an electron hole blocking layer, a first layer made from N-doped semiconductor material having a dopant concentration greater than or equal to 1018 atoms/cm3or P-doped semiconductor material, and a second layer made from semiconductor material of different nature. A lateral electric contact pad is made between the first layer and the substrate, and the material of the first layer is subjected to anodic treatment in an electrolyte.

Abstract translation: 在衬底上形成多层结构的方法包括提供连续包含电子空穴阻挡层的叠层，由具有大于或等于1018原子/ cm 3的掺杂浓度的N掺杂半导体材料或P掺杂半导体材料制成的第一层 ，以及由不同性质的半导体材料制成的第二层。 在第一层和衬底之间形成横向电接触垫，并且在电解质中对第一层的材料进行阳极处理。

公开(公告)号：US20070287257A1

公开(公告)日：2007-12-13

申请号：US11761074

申请日：2007-06-11

Applicant: Jean-Francois Damlencourt ,  Yves Morand ,  Laurent Clavelier

Inventor： Jean-Francois Damlencourt ,  Yves Morand ,  Laurent Clavelier

IPC: H01L21/336

CPC classification number: H01L21/32105 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78684

Abstract: The disclosure relates a method for producing a microelectronic device including a plurality of based Si1-yGey semi-conductor zones (where 0

Abstract translation: 本公开内容涉及一种用于生产包括多个基于Si 1-y N y Y y半导体区（其中0 半导体层（其中0

公开(公告)号：US20060276052A1

公开(公告)日：2006-12-07

申请号：US11444423

申请日：2006-06-01

Applicant: Yves Morand ,  Thierry Poiroux ,  Maud Vinet

Inventor： Yves Morand ,  Thierry Poiroux ,  Maud Vinet

IPC: H01L21/31

CPC classification number: H01L21/76251

Abstract: The method successively comprises production, on a substrate, of a stack of layers comprising at least one first layer made from germanium and silicon compound initially having a germanium concentration comprised between 10% and 50%. The first layer is arranged between second layers having germanium concentrations comprised between 0% and 10%. Then a first zone corresponding to the germanium-based element and having at least a first lateral dimension comprised between 10 nm and 500 nm is delineated by etching in said stack. Then at least lateral thermal oxidization of the first zone is performed so that a silica layer forms on the surface of the first zone and that, in the first layer, a central zone of condensed germanium forms, constituting the germanium-based element.

Abstract translation: 该方法依次包括在衬底上生产包括由锗制成的至少一个第一层和最初具有10％至5​​0％的锗浓度的硅化合物的层叠层。 第一层布置在锗浓度介于0％和10％之间的第二层之间。 然后通过在所述堆叠中的蚀刻来描绘对应于锗基元件并且具有在10nm和500nm之间的至少第一横向尺寸的第一区域。 然后，至少进行第一区域的侧向热氧化，使得在第一区域的表面上形成二氧化硅层，并且在第一层中形成构成锗基元素的浓缩锗的中心区域。

公开(公告)号：US06551930B1

公开(公告)日：2003-04-22

申请号：US09589509

申请日：2000-06-07

Applicant: Françoise Vinet ,  Yves Morand

Inventor： Françoise Vinet ,  Yves Morand

IPC: H01L21302

CPC classification number: H01L21/31144 ,  H01L21/31127 ,  H01L21/7681 ,  H01L21/76811

Abstract: A method for etching an organic dielectric material layer includes depositing an inorganic barrier layer on the organic dielectric material layer, and depositing an inorganic masking layer on the inorganic barrier layer. A masking resin layer is deposited on the inorganic masking layer. The method further includes patterning the masking resin layer and etching through the inorganic masking layer to expose the inorganic barrier layer. Remaining portions of the masking resin layer are removed, and the exposed inorganic barrier layer is etched to expose the organic dielectric material layer. The method further includes removing remaining portions of the inorganic masking layer, and etching the exposed organic dielectric material layer while using the inorganic barrier layer as a mask.

Abstract translation: 蚀刻有机介电材料层的方法包括在有机介电材料层上沉积无机阻挡层，并在无机阻挡层上沉积无机掩模层。 掩蔽树脂层沉积在无机掩模层上。 该方法还包括图案化掩模树脂层和蚀刻通过无机掩模层以露出无机阻挡层。 去除掩模树脂层的剩余部分，并且暴露的无机阻挡层被蚀刻以暴露有机介电材料层。 该方法还包括去除无机掩模层的剩余部分，并且在使用无机阻挡层作为掩模的同时蚀刻暴露的有机介电材料层。

公开(公告)号：US08877622B2

公开(公告)日：2014-11-04

申请号：US13811792

申请日：2011-07-22

Applicant: Thierry Poiroux ,  Sébastien Barnola ,  Yves Morand

Inventor： Thierry Poiroux ,  Sébastien Barnola ,  Yves Morand

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/115 ,  H01L21/768

CPC classification number: H01L21/823468 ,  H01L21/76897 ,  H01L21/823456 ,  H01L21/823475 ,  H01L27/11 ,  H01L27/11521

Abstract: A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones.

Abstract translation: 一种用于在基板表面上制造集成电路的方法，所述方法包括：在所述基板的表面上产生包括有源区和绝缘区的第一层; 在所述第一层的表面上产生栅极区域，所述栅极区域各自被绝缘间隔物包围; 产生源极/漏极; 在所述绝缘间隔物之间​​产生电介质层，所述电介质层具有与所述栅极区的上表面的上表面水平; 部分地蚀刻每个栅极区，以便降低每个栅极区的第一部分的上表面; 以及在栅极区域的第一部分上沉积绝缘介电层。

公开(公告)号：US20070105315A1

公开(公告)日：2007-05-10

申请号：US11584635

申请日：2006-10-23

Applicant: Jean-Charles Barbe ,  Laurent Clavelier ,  Benoit Vianay ,  Yves Morand

Inventor： Jean-Charles Barbe ,  Laurent Clavelier ,  Benoit Vianay ,  Yves Morand

IPC: H01L21/336

CPC classification number: H01L21/02667 ,  H01L21/02532 ,  H01L21/2022 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203

Abstract: A method according to the invention enables first and second active zones to be produced on a front face of a support, which said zones are respectively formed by first and second monocrystalline semi-conducting materials that are distinct from one another and preferably have identical crystalline structures. The front faces of the first and second active zones also present the advantage of being in the same plane. Such a method consists in particular in producing the second active zones by a crystallization step of the second semi-conducting material in monocrystalline form, from patterns made of second semi-conducting material in polycrystalline and/or amorphous form and from interface regions between said patterns and preselected first active zones. Moreover, the support is formed by stacking of a substrate and of an electrically insulating thin layer, the front face of the electrically insulating thin layer forming the front face of the support.

Abstract translation: 根据本发明的方法使得能够在支撑体的前表面上产生第一和第二活性区域，所述区域分别由彼此不同的优选具有相同晶体结构的第一和第二单晶半导体材料形成 。 第一和第二活动区域的前表面也具有处于同一平面上的优点。 这种方法特别在于通过第二半导体材料以单晶形式的结晶步骤从多晶和/或无定形形式的第二半导体材料制成的图案和由所述图案之间的界面区域产生第二活性区域 和预选的第一活动区域。 此外，通过堆叠基板和电绝缘薄层形成支撑体，电绝缘薄层的前表面形成支撑体的前表面。

公开(公告)号：US07141837B2

公开(公告)日：2006-11-28

申请号：US10817147

申请日：2004-04-02

Applicant: Philippe Coronel ,  Yves Morand ,  Thomas Skotnicki ,  Robin Cerutti

Inventor： Philippe Coronel ,  Yves Morand ,  Thomas Skotnicki ,  Robin Cerutti

IPC: H01L27/148 ,  H01L29/80

CPC classification number: H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78645 ,  H01L29/78648

Abstract: A MOS transistor formed in a silicon substrate comprising an active area surrounded with an insulating wall, a first conductive strip covering a central strip of the active area, one or several second conductive strips placed in the active area right above the first strip, and conductive regions placed in two recesses of the insulating wall and placed against the ends of the first and second strips, the silicon surfaces opposite to the conductive strips and regions being covered with an insulator forming a gate oxide.

Abstract translation: 一种形成在硅衬底中的MOS晶体管，包括被绝缘壁包围的有源区域，覆盖有源区域的中心条带的第一导电条，放置在位于第一条带正上方的有源区域中的一个或多个第二导电条，以及导电 放置在绝缘壁的两个凹部中并且抵靠第一和第二条带的端部放置的区域，与导电条带和区域相对的硅表面被形成栅极氧化物的绝缘体覆盖。