公开(公告)号：US20230137580A1

公开(公告)日：2023-05-04

申请号：US18146709

申请日：2022-12-27

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed ,  Eric M. Nequist

IPC: H01L21/822 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L27/06

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

公开(公告)号：US11557516B2

公开(公告)日：2023-01-17

申请号：US16953113

申请日：2020-11-19

Applicant: ADEIA SEMICONDUCTOR INC.

Inventor： Javier DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed ,  Eric M. Nequist

IPC: H01L23/02 ,  H01L21/822 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L27/06 ,  H01L21/768 ,  H01L23/50

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

公开(公告)号：US20250142942A1

公开(公告)日：2025-05-01

申请号：US18906050

申请日：2024-10-03

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed ,  Eric M. Nequist

IPC: H10D84/03 ,  H01L21/768 ,  H01L23/00 ,  H01L23/50 ,  H01L23/528 ,  H01L25/065 ,  H10D88/00

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.

公开(公告)号：US12142528B2

公开(公告)日：2024-11-12

申请号：US18146709

申请日：2022-12-27

Applicant: Adeia Semiconductor Inc.

Inventor： Javier A. DeLaCruz ,  Steven L. Teig ,  Ilyas Mohammed ,  Eric M. Nequist

IPC: H01L21/822 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L27/06 ,  H01L21/768 ,  H01L23/50

Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate. As further described below, the first and second dies in some embodiments are placed in a face-to-face arrangement (e.g., a vertically stacked arrangement) that has the first and second set of interconnect layers facing each other. In some embodiments, a subset of one or more interconnect layers of the second set interconnect layers of the second die has interconnect wiring that carries power, clock and/or data-bus signals that are supplied to the first IC die.