公开(公告)号：US12248869B2

公开(公告)日：2025-03-11

申请号：US18469910

申请日：2023-09-19

Applicant: Adeia Semiconductor Inc.

Inventor： Steven L. Teig ,  Kenneth Duong

IPC: G06N3/065 ,  G06F11/14 ,  G06F11/20 ,  G06N3/04 ,  G06N3/048 ,  G06N3/063 ,  G06N3/08 ,  G06N3/082 ,  G06N3/084 ,  H01L23/31 ,  H01L25/04 ,  H01L25/065 ,  H01L23/00 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H03K19/21

Abstract: Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

公开(公告)号：US11790219B2

公开(公告)日：2023-10-17

申请号：US17500374

申请日：2021-10-13

Applicant: ADEIA SEMICONDUCTOR INC.

Inventor： Steven L. Teig ,  Kenneth Duong

IPC: G06N3/065 ,  G06N3/08 ,  G06N3/04 ,  H01L25/065 ,  G06F11/20 ,  G06N3/084 ,  G06F11/14 ,  G06N3/048 ,  G06N3/063 ,  G06N3/082 ,  H01L23/31 ,  H01L23/00 ,  H01L25/075 ,  H01L25/04 ,  H01L25/11 ,  H01L25/07 ,  H03K19/21

CPC classification number: G06N3/065 ,  G06F11/1423 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/2041 ,  G06F11/2051 ,  G06N3/04 ,  G06N3/048 ,  G06N3/063 ,  G06N3/08 ,  G06N3/082 ,  G06N3/084 ,  H01L23/3128 ,  H01L25/0657 ,  G06F2201/85 ,  H01L24/16 ,  H01L24/17 ,  H01L25/043 ,  H01L25/074 ,  H01L25/0756 ,  H01L25/117 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2924/16235 ,  H03K19/21

Abstract: Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.

公开(公告)号：US20240152743A1

公开(公告)日：2024-05-09

申请号：US18469910

申请日：2023-09-19

Applicant: Adeia Semiconductor Inc.

Inventor： Steven L. Teig ,  Kenneth Duong

IPC: G06N3/065 ,  G06F11/14 ,  G06F11/20 ,  G06N3/04 ,  G06N3/048 ,  G06N3/063 ,  G06N3/08 ,  G06N3/082 ,  G06N3/084 ,  H01L23/31 ,  H01L25/065

CPC classification number: G06N3/065 ,  G06F11/1423 ,  G06F11/2007 ,  G06F11/2028 ,  G06F11/2041 ,  G06F11/2051 ,  G06N3/04 ,  G06N3/048 ,  G06N3/063 ,  G06N3/08 ,  G06N3/082 ,  G06N3/084 ,  H01L23/3128 ,  H01L25/0657 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2924/16235

Abstract: Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g., neural network) to perform particular operations (e.g., face recognition, voice recognition, etc.). For example, in some embodiments, the machine-trained parameters are weight values that are used to aggregate (e.g., to sum) several output values of several earlier stage processing nodes to produce an input value for a later stage processing node.