公开(公告)号：US20200098082A1

公开(公告)日：2020-03-26

申请号：US16138708

申请日：2018-09-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony GUTIERREZ ,  Muhammad Amber HASSAAN ,  Sooraj PUTHOOR

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/02 ,  G06F9/30

Abstract: A processing unit includes one or more processor cores and a set of registers to store configuration information for the processing unit. The processing unit also includes a coprocessor configured to receive a request to modify a memory allocation for a kernel concurrently with the kernel executing on the at least one processor core. The coprocessor is configured to modify the memory allocation by modifying the configuration information stored in the set of registers. In some cases, initial configuration information is provided to the set of registers by a different processing unit. The initial configuration information is stored in the set of registers prior to the coprocessor modifying the configuration information.

公开(公告)号：US20200089528A1

公开(公告)日：2020-03-19

申请号：US16134695

申请日：2018-09-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony GUTIERREZ ,  Sooraj PUTHOOR

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/38

Abstract: A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

公开(公告)号：US20210216368A1

公开(公告)日：2021-07-15

申请号：US17215171

申请日：2021-03-29

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony GUTIERREZ ,  Sooraj PUTHOOR

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/38

Abstract: A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

公开(公告)号：US20240303113A1

公开(公告)日：2024-09-12

申请号：US18119234

申请日：2023-03-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Anthony GUTIERREZ ,  Paul BLINZER ,  Samuel BAYLISS ,  Stephen Alexander ZEKANY ,  Ali Arda EKER

IPC: G06F9/48 ,  G06F9/38

CPC classification number: G06F9/4893 ,  G06F9/3838

Abstract: Embodiments herein describe a pull-based model to dispatch tasks in an accelerator device. That is, rather than a push-based model where a connected host pushes tasks into hardware (HW) queues in the accelerator device, the embodiments herein describe a pull-based model where a command processor (CP) loads tasks into the HW queues after any data dependencies have been resolved.

公开(公告)号：US20230196502A1

公开(公告)日：2023-06-22

申请号：US18103322

申请日：2023-01-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony GUTIERREZ ,  Muhammad Amber Hassaan ,  Sooraj Puthoor

IPC: G06T1/60 ,  G06F9/30 ,  G06F12/02 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F9/30098 ,  G06F12/023 ,  G06T1/20 ,  G06F12/02

Abstract: A processing unit includes one or more processor cores and a set of registers to store configuration information for the processing unit. The processing unit also includes a coprocessor configured to receive a request to modify a memory allocation for a kernel concurrently with the kernel executing on the at least one processor core. The coprocessor is configured to modify the memory allocation by modifying the configuration information stored in the set of registers. In some cases, initial configuration information is provided to the set of registers by a different processing unit. The initial configuration information is stored in the set of registers prior to the coprocessor modifying the configuration information.

公开(公告)号：US20220197832A1

公开(公告)日：2022-06-23

申请号：US17130604

申请日：2020-12-22

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Max RUTTENBERG ,  Vendula Venkata Srikant BHARADWAJ ,  Yasuko ECKERT ,  Anthony GUTIERREZ ,  Mark H. OSKIN

IPC: G06F13/16 ,  G11C11/4076

Abstract: A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory timing parameters for each memory module according to the module's assigned data class, thereby tailoring the memory timing parameters for efficient access of the corresponding data.

公开(公告)号：US20250028554A1

公开(公告)日：2025-01-23

申请号：US18909132

申请日：2024-10-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony GUTIERREZ ,  Sooraj PUTHOOR

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/54

Abstract: A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

公开(公告)号：US20230185742A1

公开(公告)日：2023-06-15

申请号：US18103240

申请日：2023-01-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Max RUTTENBERG ,  Vendula Venkata Srikant BHARADWAJ ,  Yasuko ECKERT ,  Anthony GUTIERREZ ,  Mark H. OSKIN

IPC: G06F13/16 ,  G11C11/4076

CPC classification number: G06F13/1668 ,  G11C11/4076

Abstract: A processor distributes memory timing parameters and data among different memory modules based upon memory access patterns. The memory access patterns indicate different types, or classes, of data for an executing workload, with each class associated with different memory access characteristics, such as different row buffer hit rate levels, different frequencies of access, different criticalities, and the like. The processor assigns each memory module to a data class and sets the memory timing parameters for each memory module according to the module’s assigned data class, thereby tailoring the memory timing parameters for efficient access of the corresponding data.

公开(公告)号：US20230185607A1

公开(公告)日：2023-06-15

申请号：US17993490

申请日：2022-11-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anthony GUTIERREZ ,  Sooraj PUTHOOR

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F9/542 ,  G06F9/545 ,  G06F9/546 ,  G06F9/3877

Abstract: A processor core is configured to execute a parent task that is described by a data structure stored in a memory. A coprocessor is configured to dispatch a child task to the at least one processor core in response to the coprocessor receiving a request from the parent task concurrently with the parent task executing on the at least one processor core. In some cases, the parent task registers the child task in a task pool and the child task is a future task that is configured to monitor a completion object and enqueue another task associated with the future task in response to detecting the completion object. The future task is configured to self-enqueue by adding a continuation future task to a continuation queue for subsequent execution in response to the future task failing to detect the completion object.

公开(公告)号：US20220197524A1

公开(公告)日：2022-06-23

申请号：US17128844

申请日：2020-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Max RUTTENBERG ,  Vedula Venkata Srikant BHARADWAJ ,  Yasuko ECKERT ,  Mark H. OSKIN ,  Anthony GUTIERREZ

IPC: G06F3/06

Abstract: A processor sets memory timing parameters based on a profile of a workload to be executed at the processor and based on a thermal budget associated with the processor. For a given workload and amount of available thermal headroom, as indicated by a detected temperature, the processor adjusts one or more of the memory timing parameters according to the workload profile. The processor is thereby able to tailor the memory timing parameters according to the memory access behavior of the workload, improving overall processing efficiency.