公开(公告)号：US20150279767A1

公开(公告)日：2015-10-01

申请号：US14722110

申请日：2015-05-26

Applicant: AMKOR TECHNOLOGY, INC.

Inventor： Kyoung Yeon Lee ,  Byong Jin Kim ,  Kyung Su Kim ,  Hyung Il Jeon ,  Jae Doo Kwon

IPC: H01L23/495 ,  H01L23/043 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/50 ,  H01L23/043 ,  H01L23/3157 ,  H01L23/49503 ,  H01L23/49861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a lead frame package structure includes a lead frame having sides that surround a die paddle and on which a plurality of leads are formed. An electronic chip is attached to the die paddle and a case is attached to the lead frame to seal the leads and the electronic chip. One or more discharge holes are formed on and extending through one or more specific leads and/or on and extending through a predetermined position of the die paddle. The discharge holes are configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the packaged electronic chip.

Abstract translation: 在一个实施例中，引线框架封装结构包括引线框架，引线框架具有围绕管芯焊盘的侧面并且在其上形成有多个引线。 将电子芯片安装在芯片上，并且将壳体附接到引线框架以密封引线和电子芯片。 一个或多个排出孔形成在一个或多个特定的引线上并且延伸穿过一个或多个特定的引线和/或延伸穿过管芯的预定位置。 排出孔被构造成排出在组装过程中形成的空气压力，从而提高封装的电子芯片的可靠性。

公开(公告)号：US10049954B2

公开(公告)日：2018-08-14

申请号：US15173379

申请日：2016-06-03

Applicant: Amkor Technology Inc.

Inventor： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Doo Kwon ,  Hyung Il Jeon

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/495 ,  H01L23/532 ,  H01L23/00 ,  H01L21/48

Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

公开(公告)号：US09633932B2

公开(公告)日：2017-04-25

申请号：US14722110

申请日：2015-05-26

Applicant: AMKOR TECHNOLOGY, INC.

Inventor： Kyoung Yeon Lee ,  Byong Jin Kim ,  Kyung Su Kim ,  Hyung Il Jeon ,  Jae Doo Kwon

IPC: H01L23/495 ,  H01L23/043 ,  H01L23/31 ,  H01L21/50 ,  H01L23/498

CPC classification number: H01L23/49541 ,  H01L21/50 ,  H01L23/043 ,  H01L23/3157 ,  H01L23/49503 ,  H01L23/49861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic package structure includes a substrate having a plurality of conductive leads. A discharge hole is disposed to extend through the substrate. An electronic chip is electrically connected to the plurality of conductive leads. A case is connected to the substrate and defines a cavity between the substrate and an upper of the case. The discharge hole and the electronic chip are disposed within the cavity, and the discharge hole is open to the outside in the electronic package structure. The discharge hole is configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the electronic package structure.

公开(公告)号：US20140042605A1

公开(公告)日：2014-02-13

申请号：US13949186

申请日：2013-07-23

Applicant: Amkor Technology, Inc.

Inventor： Kyoung Yeon Lee ,  Byong Jin Kim ,  Kyung Su Kim ,  Hyung Il Jeon ,  Jae Doo Kwon

IPC: H01L23/495 ,  H01L21/50

CPC classification number: H01L23/49541 ,  H01L21/50 ,  H01L23/043 ,  H01L23/3157 ,  H01L23/49503 ,  H01L23/49861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a lead frame package structure includes a lead frame having sides that surround a die paddle and on which a plurality of leads are formed. An electronic chip is attached to the die paddle and a case is attached to the lead frame to seal the leads and the electronic chip. One or more discharge holes are formed on and extending through one or more specific leads and/or on and extending through a predetermined position of the die paddle. The discharge holes are configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the packaged electronic chip.

Abstract translation: 在一个实施例中，引线框架封装结构包括引线框架，引线框架具有围绕管芯焊盘的侧面并且在其上形成有多个引线。 将电子芯片安装在芯片上，并且将壳体附接到引线框架以密封引线和电子芯片。 一个或多个排出孔形成在一个或多个特定的引线上并且延伸穿过一个或多个特定的引线和/或延伸穿过管芯的预定位置。 排出孔被构造成排出在组装过程中形成的空气压力，从而提高封装的电子芯片的可靠性。

公开(公告)号：US10685897B2

公开(公告)日：2020-06-16

申请号：US16032295

申请日：2018-07-11

Applicant: Amkor Technology Inc.

Inventor： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Doo Kwon ,  Hyung Il Jeon

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/495 ,  H01L21/683 ,  H01L23/498 ,  H01L23/532 ,  H01L21/48 ,  H01L23/48

Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

公开(公告)号：US20180323129A1

公开(公告)日：2018-11-08

申请号：US16032295

申请日：2018-07-11

Applicant: Amkor Technology Inc.

Inventor： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Doo Kwon ,  Hyung Il Jeon

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L23/532 ,  H01L21/48

Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

公开(公告)号：US20170069558A1

公开(公告)日：2017-03-09

申请号：US15173379

申请日：2016-06-03

Applicant: Amkor Technology, Inc.

Inventor： Won Bae Bang ,  Byong Jin Kim ,  Gi Jeong Kim ,  Jae Doo Kwon ,  Hyung Il Jeon

IPC: H01L23/31 ,  H01L21/52 ,  H01L23/29 ,  H01L23/495 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/3128 ,  H01L21/4839 ,  H01L21/4846 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/48 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49558 ,  H01L23/49579 ,  H01L23/49586 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/562 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L24/91 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/05026 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/8385 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

Abstract translation: 封装的半导体器件包括具有表面光洁度层的可路由模制引线框架结构。 在一个实施例中，可路由模制的引线框架结构包括包括表面光洁度层的第一层压层，连接到表面光洁度层的通孔和覆盖露出的表面光洁度层顶表面的通孔的第一树脂层。 第二层叠层包括连接到通孔的第二导电图案，连接到第二导电图案的凸块焊盘以及覆盖第一树脂层的一侧的第二树脂层，第二导电图案和凸块焊盘。 半导体管芯与表面处理层电连接，密封剂覆盖半导体管芯和第一树脂层的另一侧。 表面光洁度层提供可定制和改进的接合结构，用于将半导体管芯连接到可路由的模制引线框架结构。

公开(公告)号：US09054089B2

公开(公告)日：2015-06-09

申请号：US13949186

申请日：2013-07-23

Applicant: Amkor Technology, Inc.

Inventor： Kyoung Yeon Lee ,  Byong Jin Kim ,  Kyung Su Kim ,  Hyung Il Jeon ,  Jae Doo Kwon

IPC: H01L23/495 ,  H01L21/50 ,  H01L23/498

CPC classification number: H01L23/49541 ,  H01L21/50 ,  H01L23/043 ,  H01L23/3157 ,  H01L23/49503 ,  H01L23/49861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a lead frame package structure includes a lead frame having sides that surround a die paddle and on which a plurality of leads are formed. An electronic chip is attached to the die paddle and a case is attached to the lead frame to seal the leads and the electronic chip. One or more discharge holes are formed on and extending through one or more specific leads and/or on and extending through a predetermined position of the die paddle. The discharge holes are configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the packaged electronic chip.

Abstract translation: 在一个实施例中，引线框架封装结构包括引线框架，引线框架具有围绕管芯焊盘的侧面并且在其上形成有多个引线。 将电子芯片安装在芯片上，并且将壳体附接到引线框架以密封引线和电子芯片。 一个或多个排出孔形成在一个或多个特定的引线上并且延伸穿过一个或多个特定的引线和/或延伸穿过管芯的预定位置。 排出孔被构造成排出在组装过程中形成的空气压力，从而提高封装的电子芯片的可靠性。