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    Synchronizing data transfer from a core to a physical interface
    3.
    发明授权
    Synchronizing data transfer from a core to a physical interface 有权
    同步从核心到物理接口的数据传输

    公开(公告)号：US09037893B2

    公开(公告)日：2015-05-19

    申请号：US13852625

    申请日：2013-03-28

    Applicant: ANALOG DEVICES, INC.

    Inventor： Brian Holford ,  Matthew D. McShea

    IPC: G06F1/00 ,  G06F1/04 ,  G06F1/24 ,  G06F5/06 ,  G06F13/42 ,  H04B1/00 ,  H04J3/06

    CPC classification number: G06F1/04 ,  G06F1/24 ,  G06F3/05 ,  G06F13/4243 ,  H04B1/00 ,  H04J3/0685

    Abstract: In one example implementation, the present disclosure provides a system that includes circuitry and one or more electronic components for synchronizing data transfer from a core to a physical interface. One example can involve an apparatus for interfacing a digital core with at least one physical interface that includes a macro configured on the digital core, the macro having at least one data output, a first data input, a reset input and a sync reset output, the macro to be clocked by a first clock having a first clock rate. The first clock can be configured to clock in data from the digital core on the first data input; clock in a reset signal from the digital core on the reset input, wherein a synchronized reset signal is output on the sync reset output. The apparatus can also include physical interface circuitry and a reset sampling input.

    Abstract translation: 在一个示例实现中，本公开提供了一种系统，其包括用于同步从核到物理接口的数据传输的电路和一个或多个电子组件。 一个示例可以涉及用于将数字核与至少一个物理接口进行接口的装置，所述物理接口包括配置在数字内核上的宏，所述宏具有至少一个数据输出，第一数据输入，复位输入和同步复位输出， 由具有第一时钟速率的第一时钟计时的宏。 第一个时钟可以配置为在第一个数据输入端从数字核心的数据进行时钟; 来自复位输入上的数字内核的复位信号中的时钟，其中在同步复位输出上输出同步的复位信号。 该装置还可以包括物理接口电路和复位采样输入。

    FREQUENCY SYNTHESIZER WITH DYNAMIC PHASE AND PULSE-WIDTH CONTROL
    6.
    发明申请
    FREQUENCY SYNTHESIZER WITH DYNAMIC PHASE AND PULSE-WIDTH CONTROL 有权
    具有动态相位和脉冲宽度控制的频率合成器

    公开(公告)号：US20160277030A1

    公开(公告)日：2016-09-22

    申请号：US14741984

    申请日：2015-06-17

    Applicant: ANALOG DEVICES, INC.

    Inventor： Oscar Sebastian Burbano ,  Matthew D. McShea ,  Peter Derounian ,  Reuben P. Nelson ,  Ziwei Zheng ,  Brad P. Jeffries

    IPC: H03K23/40 ,  H03L7/06

    CPC classification number: H03K23/40 ,  G06F1/022 ,  H03K21/00 ,  H03K21/38 ,  H03K23/00 ,  H03K23/58 ,  H03K23/662 ,  H03K23/665

    Abstract: An agile frequency synthesizer with dynamic phase and pulse-width control is disclosed. In one aspect, the frequency synthesizer includes a count circuit configured to modify a stored count value by an adjustment value. The frequency synthesizer also includes an output clock generator configured to generate an output clock signal having rising and falling edges that are based at least in part on the stored count value satisfying a count threshold. The count circuit is further configured to alter at least one of the period or phase of the output clock signal based at least in part on modifying an adjustment rate of the count circuit.

    Abstract translation: 公开了一种具有动态相位和脉冲宽度控制的敏捷频率合成器。 一方面，频率合成器包括：计数电路，被配置为通过调整值来修改存储的计数值。 频率合成器还包括输出时钟发生器，其被配置为产生具有上升沿和下降沿的输出时钟信号，所述上升沿和下降沿至少部分地基于满足计数阈值的所存储的计数值。 计数电路还被配置为至少部分地改变计数电路的调整速率来改变输出时钟信号的周期或相位中的至少一个。

    SYNCHRONIZING DATA TRANSFER FROM A CORE TO A PHYSICAL INTERFACE
    8.
    发明申请
    SYNCHRONIZING DATA TRANSFER FROM A CORE TO A PHYSICAL INTERFACE 有权
    将数据从核心同步到物理接口

    公开(公告)号：US20140281654A1

    公开(公告)日：2014-09-18

    申请号：US13852625

    申请日：2013-03-28

    Applicant: ANALOG DEVICES, INC.

    Inventor： Brian Holford ,  Matthew D. McShea

    IPC: G06F1/04 ,  G06F1/24

    CPC classification number: G06F1/04 ,  G06F1/24 ,  G06F3/05 ,  G06F13/4243 ,  H04B1/00 ,  H04J3/0685

    Abstract: In one example implementation, the present disclosure provides a system that includes circuitry and one or more electronic components for synchronizing data transfer from a core to a physical interface. One example can involve an apparatus for interfacing a digital core with at least one physical interface that includes a macro configured on the digital core, the macro having at least one data output, a first data input, a reset input and a sync reset output, the macro to be clocked by a first clock having a first clock rate. The first clock can be configured to clock in data from the digital core on the first data input; clock in a reset signal from the digital core on the reset input, wherein a synchronized reset signal is output on the sync reset output. The apparatus can also include physical interface circuitry and a reset sampling input.

    Abstract translation: 在一个示例实现中，本公开提供了一种系统，其包括用于同步从核到物理接口的数据传输的电路和一个或多个电子组件。 一个示例可以涉及用于将数字核与至少一个物理接口进行接口的装置，所述物理接口包括配置在数字内核上的宏，所述宏具有至少一个数据输出，第一数据输入，复位输入和同步复位输出， 由具有第一时钟速率的第一时钟计时的宏。 第一个时钟可以配置为在第一个数据输入端从数字核心的数据进行时钟; 来自复位输入上的数字内核的复位信号中的时钟，其中在同步复位输出上输出同步的复位信号。 该装置还可以包括物理接口电路和复位采样输入。

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