公开(公告)号：US12253410B2

公开(公告)日：2025-03-18

申请号：US17575584

申请日：2022-01-13

Applicant: ANPEC ELECTRONICS CORPORATION

Inventor： Jia-Hua Hong

IPC: G01J1/42

Abstract: A method of improving performance of an averager is provided. The method includes steps of: (a) multiplying a value of a (n−1)th piece of output data by a value “N” to calculate a temporary value; (b) determining whether or not a difference between an nth piece of input data and the (n−1)th piece of output data is larger than or smaller than a zero value, if yes, compensating the temporary value to obtain a correction value and performing step (c), if no, setting the correction value and performing step (c); (c) dividing the correction value by the value “N” to obtain a first value; (d) subtracting the first value from the correction value and adding up the correction value and the nth piece of input data to obtain a second value; and (e) dividing the second value by the value “N” to calculate an output value of the averager.

公开(公告)号：US20210405095A1

公开(公告)日：2021-12-30

申请号：US17035984

申请日：2020-09-29

Applicant: ANPEC ELECTRONICS CORPORATION

Inventor： Jia-Hua Hong

IPC: G01R19/165 ,  H03F3/45

Abstract: A rapid sensing value estimation circuit and a method thereof are provided. The circuit includes a first sensing unit, an integration sensing circuit and a rapid estimation circuit. The rapid estimation circuit includes a clock generator, a second counter, a first digital comparator, an arithmetic module and a remainder calculation module. The clock generator generates a clock signal with a first frequency. The second counter counts the clock signal within the integration time to generate a second count value. The first digital comparator determines whether the second count value exceeds a first predetermined count value when the first count value increases. The arithmetic module calculates an estimated count value result and a remainder, and the remainder calculation module can further calculate and estimate values of decimal places of this signal based on the remainder.

公开(公告)号：US20240035882A1

公开(公告)日：2024-02-01

申请号：US17950217

申请日：2022-09-22

Applicant: ANPEC ELECTRONICS CORPORATION

Inventor： YU-YU CHEN ,  Jia-Hua Hong ,  CHIH-YUAN CHEN

IPC: G01J1/16 ,  G01J1/42

CPC classification number: G01J1/16 ,  G01J1/4204 ,  G01J2001/1668 ,  G01J1/08

Abstract: A light sensing method having a sensing order adjusting mechanism is provided. The method includes steps of: in a previous sensing cycle, sensing a first light signal that is emitted by both of an ambient light source and a light-emitting component and then is reflected by a tested object; in the previous sensing cycle, sensing a second light signal that is emitted by both of the ambient light source and the light-emitting component and then is reflected by the tested object; in the previous sensing cycle, sensing an ambient light signal emitted by only the ambient light source; and in a next sensing cycle, sensing the first light signal, the second light signal and the ambient light signal in an order different from that in the previous sensing cycle.

公开(公告)号：US11573556B2

公开(公告)日：2023-02-07

申请号：US17141161

申请日：2021-01-04

Applicant: ANPEC ELECTRONICS CORPORATION

Inventor： Yu-Wen Wang ,  Jia-Hua Hong

IPC: H03G1/00 ,  G05B19/4155 ,  G01R27/28 ,  H03G3/00

Abstract: A signal gain determination circuit including a digital comparator, a digital controller and an arithmetic module, and a signal gain determination method are provided. A sensing integration circuit generates a first count during a first integration time according to a first sensing signal. The digital comparator compares the first count and a predetermined count to generate a comparison result. The digital controller generates a control signal for indicating a signal gain to a signal amplifier of the sensing integration circuit according to the comparison result. The signal amplifier adjusts the first sensing signal according to the signal gain to generate a second sensing signal, so that the sensing integration circuit generates a second count corresponding to the second sensing signal during a second integration time. The arithmetic module generates an output count corresponding to the first sensing signal according to the second count and the signal gain.

公开(公告)号：US11476844B1

公开(公告)日：2022-10-18

申请号：US17549872

申请日：2021-12-14

Applicant: ANPEC ELECTRONICS CORPORATION

Inventor： Jia-Hua Hong

IPC: H03K5/00 ,  H03K5/1252 ,  H03K3/013

Abstract: A method of stabilizing data of digital signals is provided. The method includes steps of: (a) determining whether or not next input data is larger than previous output data, if yes, adding a base value to a trend value and then performing step(c), if no, performing step(b); (b) determining whether or not the next input data is smaller than the previous output data, if yes, subtracting the base value from the trend value and performing step(c), if no, performing step(c); (c) determining whether or not the trend value is larger than a positive threshold, if yes, subtracting a trend correction coefficient from the previous output data, if no, performing step(d); and (d) determining whether or not the trend value is smaller than a negative threshold, if yes, adding the trend correction coefficient to the previous output data; if no, outputting the previous output data.

公开(公告)号：US11630134B2

公开(公告)日：2023-04-18

申请号：US17035984

申请日：2020-09-29

Applicant: ANPEC ELECTRONICS CORPORATION

Inventor： Jia-Hua Hong

IPC: G01R19/165 ,  H03F3/45

Abstract: A rapid sensing value estimation circuit and a method thereof are provided. The circuit includes a first sensing unit, an integration sensing circuit and a rapid estimation circuit. The rapid estimation circuit includes a clock generator, a second counter, a first digital comparator, an arithmetic module and a remainder calculation module. The clock generator generates a clock signal with a first frequency. The second counter counts the clock signal within the integration time to generate a second count value. The first digital comparator determines whether the second count value exceeds a first predetermined count value when the first count value increases. The arithmetic module calculates an estimated count value result and a remainder, and the remainder calculation module can further calculate and estimate values of decimal places of this signal based on the remainder.

公开(公告)号：US20220333983A1

公开(公告)日：2022-10-20

申请号：US17392263

申请日：2021-08-03

Applicant: ANPEC ELECTRONICS CORPORATION

Inventor： Jia-Hua Hong ,  CHIH-HENG SU

IPC: G01J1/44 ,  G01J1/42

Abstract: A method of stabilizing data of digital signals is provided. The method includes steps of: setting a boundary coefficient; reading a piece of digital data; defining a value of the piece of digital data as a center value; outputting the value of the piece of digital data; reading a next piece of digital data; subtracting a value of the next piece of digital data from the previously outputted value to obtain a positive difference or a negative difference; and determining whether or not an absolute value of the positive or negative difference is larger than the boundary coefficient, if not, outputting the center value, if yes, updating the center value such that the updated center value is equal to the value of the next piece of digital data, and outputting the updated center value.

公开(公告)号：US20220083028A1

公开(公告)日：2022-03-17

申请号：US17141161

申请日：2021-01-04

Applicant: ANPEC ELECTRONICS CORPORATION

Inventor： YU-WEN WANG ,  Jia-Hua Hong

IPC: G05B19/4155

Abstract: A signal gain determination circuit including a digital comparator, a digital controller and an arithmetic module, and a signal gain determination method are provided. A sensing integration circuit generates a first count during a first integration time according to a first sensing signal. The digital comparator compares the first count and a predetermined count to generate a comparison result. The digital controller generates a control signal for indicating a signal gain to a signal amplifier of the sensing integration circuit according to the comparison result. The signal amplifier adjusts the first sensing signal according to the signal gain to generate a second sensing signal, so that the sensing integration circuit generates a second count corresponding to the second sensing signal during a second integration time. The arithmetic module generates an output count corresponding to the first sensing signal according to the second count and the signal gain.

公开(公告)号：US12253409B2

公开(公告)日：2025-03-18

申请号：US17950217

申请日：2022-09-22

Applicant: ANPEC ELECTRONICS CORPORATION

Inventor： Yu-Yu Chen ,  Jia-Hua Hong ,  Chih-Yuan Chen

IPC: G01J1/16 ,  G01J1/42 ,  G01J1/08

Abstract: A light sensing method having a sensing order adjusting mechanism is provided. The method includes steps of: in a previous sensing cycle, sensing a first light signal that is emitted by both of an ambient light source and a light-emitting component and then is reflected by a tested object; in the previous sensing cycle, sensing a second light signal that is emitted by both of the ambient light source and the light-emitting component and then is reflected by the tested object; in the previous sensing cycle, sensing an ambient light signal emitted by only the ambient light source; and in a next sensing cycle, sensing the first light signal, the second light signal and the ambient light signal in an order different from that in the previous sensing cycle.

公开(公告)号：US12078540B2

公开(公告)日：2024-09-03

申请号：US17979862

申请日：2022-11-03

Applicant: ANPEC ELECTRONICS CORPORATION

Inventor： Jia-Hua Hong

IPC: G01J3/50

CPC classification number: G01J3/50

Abstract: An optical sensor having a common light sensing circuit for synchronously sensing a plurality of color light signals is provided. A plurality of photoelectric components respectively convert the plurality of color light signals into a plurality of photocurrents. A plurality of gain amplifiers respectively multiply the plurality of photocurrents by a plurality of gains to output a plurality of amplified photocurrents. An arithmetic circuit adds up the plurality of amplified photocurrents to output a total amplified photocurrent signal. A common analog-to-digital converter converts the total amplified photocurrent signal into a digital signal. A counter circuit counts bit values of the digital signal to output a counting signal.