公开(公告)号：US4382975A

公开(公告)日：1983-05-10

申请号：US283581

申请日：1981-07-15

Applicant: Addison B. Jones

Inventor： Addison B. Jones

IPC: C23C14/24 ,  C23C14/26 ,  C23C13/02

CPC classification number: C23C14/26 ,  C23C14/246

Abstract: The invention is a thin film alloy source utilizing a supply of alloy wire selected for deposition onto a substrate. The wire is advanced through an induction heating means at a controlled rate for evaporation onto the substrate. Detection of the meniscus height or temperature of the end of the wire being evpaorated yields a control signal for operating the control wire feed mechanism for advancing the wire at a rate to provide a predetermined coating thickness.

Abstract translation: 本发明是一种利用选择用于沉积到基底上的合金丝供应的薄膜合金源。 导线以受控的速率通过感应加热装置前进，以蒸发到基底上。 所检测的弯管液面的高度或末端的温度被控制，产生一个控制信号，用于操作控制丝进给机构，以提供预定涂层厚度的丝线。

公开(公告)号：US5440162A

公开(公告)日：1995-08-08

申请号：US280417

申请日：1994-07-26

Applicant: Eugene R. Worley ,  Addison B. Jones ,  Rajiv Gupta

Inventor： Eugene R. Worley ,  Addison B. Jones ,  Rajiv Gupta

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L29/06 ,  H02H9/00

CPC classification number: H01L27/0251

Abstract: An ESD protection circuit for the pads of an integrated circuit (IC) using silicide-clad diffusions is disclosed. The circuit uses a robust N+ diode with N-well block, an output NFET and a large transient clamp, each with a distributed, integrated N-well drain resistor to prevent the IC from avalanching and leakage during the Human Body Model and Charged Device Model tests for ESD.

Abstract translation: 公开了一种使用硅化物包层扩散的集成电路（IC）的焊盘的ESD保护电路。 该电路使用具有N阱块的鲁棒N +二极管，输出NFET和大型瞬态钳位，每个具有分布式集成的N阱漏极电阻，以防止IC在人体模型和充电器件模型中出现雪崩和泄漏 ESD测试。

公开(公告)号：US4357364A

公开(公告)日：1982-11-02

申请号：US257822

申请日：1981-04-27

Applicant: Addison B. Jones

Inventor： Addison B. Jones

IPC: H01L21/027 ,  G03F7/20 ,  G03F7/38 ,  B05D3/06

CPC classification number: G03F7/2059 ,  Y10S438/942

Abstract: An improvement in the method of forming polymerization resists by directing high energy particles such as electron beams along a path across a vacuum chamber and onto polymerizable molecular species at a substrate surface with sufficient energy to polymerize the polymerizable molecular species in situ is provided, comprising maintaining a chamber-isolated relatively higher pressure layer of polymerizable molecular species vapor locally at the substrate surface during, e.g. electron beam exposure to form the resist while maintaining the beam path free of polymerizable molecular species during beam traverse of the chamber. Polymerization resist generation apparatus is also provided comprising a high energy particle, e.g. electron beam source including an electron beam gun and a vacuum chamber therebeyond, means adapted to support a substrate having a surface on which a resist is to be generated in electron beam exposed relation, means defining a closed volume between the supported substrate and the electron beam source, and means to introduce polymerizable molecular species vapor into the closed volume for electron beam exposure and polymerization in situ on the substrate surface.

Abstract translation: 提供形成聚合反应的方法的改进通过沿着穿过真空室的路径引导高能粒子（例如电子束），并在基底表面上以足够的能量原位聚合可聚合分子物质来提供抗性，其包括维持 在例如室温下，在衬底表面局部存在可分离的可聚合分子种类的蒸气相对较高的压力层 电子束曝光以形成抗蚀剂，同时在室的光束穿过期间保持光束路径不含可聚合分子物质。 还提供聚合抗蚀剂生成装置，其包括高能粒子，例如， 包括电子束枪和其中的真空室的电子束源，适于支撑具有电子束暴露关系在其上产生抗蚀剂的表面的衬底的装置，在支撑衬底和电子束之间限定封闭体积的装置 来源和将可聚合分子物质蒸气引入封闭体积中以便在基底表面上原位电子束暴露和聚合的手段。

公开(公告)号：US4339305A

公开(公告)日：1982-07-13

申请号：US231712

申请日：1981-02-05

Applicant: Addison B. Jones

Inventor： Addison B. Jones

IPC: H01F41/34 ,  H01L21/48 ,  H05K1/03 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/24 ,  H05K3/46 ,  B44C1/22 ,  B29C17/08 ,  C03C15/00 ,  C03C25/06

CPC classification number: H01L21/4846 ,  H01F41/34 ,  H05K3/107 ,  H05K1/0306 ,  H05K2201/0347 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2203/072 ,  H05K3/002 ,  H05K3/0041 ,  H05K3/048 ,  H05K3/244 ,  H05K3/4661

Abstract: The method of manufacturing predetermined microcircuit conductor patterns, which includes forming on the surface plane of a substrate a layer of insulator material, forming a layer of resist on the layer of insulator material, patterning the layer of resist to define a channel pattern, etching the channel pattern with relatively overwide channels, conditioning the channel bases to receive plating material, and thereafter filling the overwide channels with the plating material to a height at least substantially co-planar with the insulator material to define the predetermined conductor patterns, removing the mask and plated material thereon to uncover completely the conductor pattern.

Abstract translation: 制造预定微电路导体图案的方法包括在绝缘体材料层上形成绝缘体材料层，在绝缘体材料层上形成抗蚀剂层，图案化抗蚀剂层以限定沟道图案，蚀刻 通道图案具有相对超范围的通道，调节通道基底以接收电镀材料，然后用电镀材料填充超宽通道至与绝缘体材料至少基本共面的高度，以限定预定导体图案，去除掩模和 在其上镀覆材料以完全揭露导体图案。

公开(公告)号：US4326936A

公开(公告)日：1982-04-27

申请号：US195957

申请日：1980-10-14

Applicant: Addison B. Jones

Inventor： Addison B. Jones

IPC: H01F41/34 ,  C23C15/00

CPC classification number: H01F41/34

Abstract: The invention is a method of sloping thin film materials so that smooth, continuous films may be deposited thereon. By controlling the thickness of resist mask over the materials (as for patterning) relative to ion milling or sputter etching parameters, repeatable slopes and linewidths may be achieved. For use in bubble memory fabrication, the sloping of conductor walls enables propagation bars to be laid down in crossing over relation thereto while enhancing yield.

Abstract translation: 本发明是一种倾斜薄膜材料的方法，从而可以在其上沉积光滑的连续薄膜。 通过相对于离子研磨或溅射蚀刻参数控制材料（如图案化）上的抗蚀剂掩模的厚度，可以实现可重复的斜率和线宽。 为了在气泡存储器制造中使用，导体壁的倾斜使得传播条可以在与之相关的同时放置，同时提高产量。

公开(公告)号：US4459937A

公开(公告)日：1984-07-17

申请号：US397646

申请日：1982-07-12

Applicant: Addison B. Jones

Inventor： Addison B. Jones

IPC: G03F7/20 ,  C23C13/08

CPC classification number: G03F7/2059

Abstract: An improvement in the method of forming polymerization resists by directing high energy particles such as electron beams along a path across a vacuum chamber and onto polymerizable molecular species at a substrate surface with sufficient energy to polymerize the polymerizable molecular species in situ is provided, comprising maintaining a chamber-isolated relatively higher pressure layer of polymerizable molecular species vapor locally at the substrate surface during, e.g. electron beam exposure to form the resist while maintaining the beam path free of polymerizable molecular species during beam traverse of the chamber. Polymerization resist generation apparatus is also provided comprising a high energy particle, e.g. electron beam source including an electron beam gun and a vacuum chamber therebeyond, means adapted to support a substrate having a surface on which a resist is to be generated in electron beam exposed relation, means defining a closed volume between the supported substrate and the electron beam source, and means to introduce polymerizable molecular species vapor into the closed volume for electron beam exposure and polymerization in situ on the substrate surface.

Abstract translation: 提供形成聚合反应的方法的改进通过沿着穿过真空室的路径引导高能粒子（例如电子束），并在基底表面上以足够的能量原位聚合可聚合分子物质来提供抗性，其包括维持 在例如室温下，在衬底表面局部存在可分离的可聚合分子种类的蒸气相对较高的压力层 电子束曝光以形成抗蚀剂，同时在室的光束穿过期间保持光束路径不含可聚合分子物质。 还提供聚合抗蚀剂生成装置，其包括高能粒子，例如， 包括电子束枪和其中的真空室的电子束源，适于支撑具有电子束暴露关系在其上产生抗蚀剂的表面的衬底的装置，在支撑衬底和电子束之间限定封闭体积的装置 来源和将可聚合分子物质蒸气引入封闭体积中以便在基底表面上原位电子束暴露和聚合的手段。

公开(公告)号：US4432134A

公开(公告)日：1984-02-21

申请号：US376483

申请日：1982-05-10

Applicant: Addison B. Jones ,  Francis M. Erdmann

Inventor： Addison B. Jones ,  Francis M. Erdmann

IPC: H01L39/24 ,  H01L39/22

CPC classification number: H01L39/2493 ,  Y10S505/82 ,  Y10S505/922 ,  Y10T29/49014

Abstract: A method of forming a superconductor-barrier-superconductor junction device by the steps of depositing a first superconductive layer on a substrate, forming a barrier layer on the first superconductive layer and depositing a second superconductive layer on the barrier layer. A layer of photoresist is then deposited over the second superconductive layer and patterned together with the second superconductive layer to form a mesa structure. A dielectric layer is deposited over the mesa structure, and the photoresist layer portion is dissolved thereby lifting off the dielectric portion overlying said second superconductive layer portion.

Abstract translation: 通过以下步骤形成超导体 - 阻挡 - 超导体结器件的方法：在衬底上沉积第一超导层，在第一超导层上形成阻挡层，并在阻挡层上沉积第二超导层。 然后将一层光致抗蚀剂沉积在第二超导层上，并与第二超导层一起构图以形成台面结构。 介电层沉积在台面结构的上方，并且光致抗蚀剂层部分被溶解，从而提升覆盖在所述第二超导层部分上的电介质部分。

公开(公告)号：US4368689A

公开(公告)日：1983-01-18

申请号：US220397

申请日：1980-12-29

Applicant: Addison B. Jones

Inventor： Addison B. Jones

IPC: C23C14/14 ,  C23C14/24 ,  C23C14/30 ,  C23C14/54 ,  C23C13/02

CPC classification number: C23C14/30 ,  C23C14/246

Abstract: The invention is an apparatus and method for achieving thin film deposition, of uniform composition, from evaporated alloys. A source of wire alloy, selected for the particular thin film deposition on a substrate, is continuously fed through a region of high speed electron bombardment confined to an end of the wire, for evaporation of the wire in the vicinity of the substrate. An ion flux detector controls the rate of feeding of the wire source in accordance with the detected flux to lay down a uniform thin film of predetermined thickness. A high potential is established between the wire and the source of the electrons and the liberated electrons are guided by the electric field toward the end of the wire being evaporated, which serves as an anode.

Abstract translation: 本发明是从蒸发的合金中获得均匀组成的薄膜沉积的装置和方法。 选择用于在衬底上的特定薄膜沉积的线合金源被连续馈送通过限定在线的端部的高速电子轰击区域，用于在衬底附近蒸发线。 离子通量检测器根据检测的通量来控制送丝源的供给速率，以放置预定厚度的均匀薄膜。 在电线和电子源之间建立高电位，并且释放的电子被电场引导到被蒸发的线的端部，其用作阳极。

公开(公告)号：US4337132A

公开(公告)日：1982-06-29

申请号：US206929

申请日：1980-11-14

Applicant: Addison B. Jones

Inventor： Addison B. Jones

IPC: C23C14/35 ,  C23F4/00 ,  H01L21/311 ,  H01L21/3213 ,  C23C15/00 ,  C23F1/00

CPC classification number: H01L21/31138 ,  C23C14/35 ,  C23F4/00 ,  H01L21/32131

Abstract: The invention is a method of minimizing redeposition of thin film material being removed by ion impact via a patterned resist mask, which invention determines the resist mask etching rates in selected atmospheres and determines the material etching rates in selected atmospheres. Then the mask thickness is selected relative to the material thickness, the ambient gases, and the ion beam parameters to cause the resist mask to be faceted to the edges of underlying material as the unprotected layer is removed such that no resist walls remain to receive redeposited material. A different embodiment of the invention employes a getter mask material between the resist mask and said material where the thickness and etching rates of resist, said material and getter material are relatively selected to cause the unprotected getter material to be removed shortly prior to faceting of the resist down to the protected getter material in a first environment, and continues etching the thin film material in a different environment which also causes resist removal while eroding the getter mask very slowly. The getter mask can thus be very thin to minimize redeposition.

Abstract translation: 本发明是通过图案化的抗蚀剂掩模使离子冲击除去的薄膜材料的再沉积最小化的方法，该方法确定了选定气氛中的抗蚀剂掩模蚀刻速率，并确定了所选择的气氛中的材料蚀刻速率。 然后，相对于材料厚度，环境气体和离子束参数选择掩模厚度，以使抗蚀剂掩模被切面到下层材料的边缘，因为未被保护的层被去除，使得不存在抗蚀剂壁以接收再沉积 材料。 本发明的不同实施例在抗蚀剂掩模和所述材料之间采用吸气剂掩模材料，其中相对地选择抗蚀剂，所述材料和吸气材料的厚度和蚀刻速率，以使得不受保护的吸气剂材料在短时间之前被去除 在第一环境中抵抗受保护的吸气剂材料，并且在不同的环境中继续蚀刻薄膜材料，这也使得除去吸气剂掩模之前非常缓慢地进行抗蚀剂去除。 因此，吸气面罩可以非常薄以最小化再沉积。

公开(公告)号：US4536882A

公开(公告)日：1985-08-20

申请号：US119331

申请日：1980-02-07

Applicant: Addison B. Jones ,  Siegfried G. Plonski

Inventor： Addison B. Jones ,  Siegfried G. Plonski

IPC: G03F1/00 ,  G03F1/22 ,  G21C11/00 ,  B05B5/00 ,  G02B5/00

CPC classification number: G03F1/22

Abstract: A mask which is especially useful in X-ray lithography wherein the X-ray absorber material is embedded in the mask membrane.

Abstract translation: 在X射线光刻中特别有用的掩模，其中X射线吸收材料嵌入掩模膜中。