公开(公告)号：US20180366328A1

公开(公告)日：2018-12-20

申请号：US15988854

申请日：2018-05-24

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Minrui YU ,  Mehul B. NAIK

IPC: H01L21/285 ,  H01L21/768 ,  H01L23/532 ,  H01L21/67

CPC classification number: H01L21/2855 ,  C23C14/0682 ,  C23C14/3464 ,  C23C14/352 ,  H01J37/3417 ,  H01J37/3429 ,  H01J37/3435 ,  H01J37/3447 ,  H01L21/32053 ,  H01L21/67138 ,  H01L21/76877 ,  H01L23/53209 ,  H01L23/53271

Abstract: Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.

公开(公告)号：US20210143323A1

公开(公告)日：2021-05-13

申请号：US16681351

申请日：2019-11-12

Applicant: Applied Materials, Inc.

Inventor： Jong Mun KIM ,  Minrui YU ,  Chando PARK ,  Mang-Mang LING ,  Jaesoo AHN ,  Chentsau Chris YING ,  Srinivas D. NEMANI ,  Mahendra PAKALA ,  Ellie Y. YIEH

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a method for forming a magnetic tunnel junction (MTJ) device structure includes performing a patterning process by an ion beam etching process in a processing chamber to pattern a film stack disposed on a substrate, wherein the film stack comprises a reference layer, a tunneling barrier layer and a free layer disposed on the tunneling barrier, and determining an end point for the patterning process.

公开(公告)号：US20230389441A1

公开(公告)日：2023-11-30

申请号：US18231414

申请日：2023-08-08

Applicant: Applied Materials, Inc.

Inventor： Minrui YU ,  Wenhui WANG ,  Jaesoo AHN ,  Jong Mun KIM ,  Sahil PATEL ,  Lin XUE ,  Chando PARK ,  Mahendra PAKALA ,  Chentsau Chris YING ,  Huixiong DAI ,  Christopher S. NGAI

IPC: H10N50/10 ,  G01R33/09 ,  G11C11/16 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10N50/10 ,  G01R33/098 ,  G11C11/161 ,  G01R33/095 ,  H10B61/00 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

公开(公告)号：US20190311908A1

公开(公告)日：2019-10-10

申请号：US16366539

申请日：2019-03-27

Applicant: Applied Materials, Inc.

Inventor： He REN ,  Maximillian CLEMONS ,  Mei-Yee SHEK ,  Minrui YU ,  Bencherki MEBARKI ,  Mehul B. NAIK ,  Chentsau YING ,  Srinivas D. NEMANI

IPC: H01L21/285 ,  H01L29/45

Abstract: Methods for forming low resistivity metal silicide interconnects using one or a combination of a physical vapor deposition (PVD) process and an anneal process are described herein. In one embodiment, a method of forming a plurality of wire interconnects includes flowing a sputtering gas into a processing volume of a processing chamber, applying a power to a target disposed in the processing volume, forming a plasma in a region proximate to the sputtering surface of the target, and depositing the metal and silicon layer on the surface of the substrate. Herein, the first target comprises a metal silicon alloy and a sputtering surface thereof is angled with respect to a surface of the substrate at between about 10° and about 50°.

公开(公告)号：US20160372330A1

公开(公告)日：2016-12-22

申请号：US14745367

申请日：2015-06-19

Applicant: Applied Materials, Inc.

Inventor： Minrui YU ,  Kai MA ,  Thomas KWON ,  Kaushal K. SINGH ,  Er-Xuan PING

IPC: H01L21/285 ,  C23C16/06 ,  H01L23/532 ,  C23C28/00 ,  H01L21/768 ,  C23C14/06 ,  C23C14/16

CPC classification number: H01L23/53266 ,  C23C14/0641 ,  C23C16/401 ,  C23C28/322 ,  C23C28/34 ,  C23C28/345 ,  H01L21/76838

Abstract: The present disclosure provides a film stack structure formed on a substrate and methods for forming the film stack structure on the substrate. In one embodiment, the method for forming a film stack structure on a substrate includes depositing a first adhesion layer on an oxide layer formed on the substrate and depositing a metal layer on the first adhesion layer, wherein the first adhesion layer and the metal layer form a stress neutral structure.

Abstract translation: 本公开提供了一种形成在基板上的薄膜叠层结构以及在该基板上形成薄膜叠层结构的方法。 在一个实施例中，用于在衬底上形成膜堆叠结构的方法包括在形成在衬底上的氧化物层上沉积第一粘附层并在第一粘合层上沉积金属层，其中第一粘附层和金属层形成 应力中性结构。