公开(公告)号：US11638376B2

公开(公告)日：2023-04-25

申请号：US17686850

申请日：2022-03-04

Applicant: Applied Materials, Inc.

Inventor： Russell Chin Yee Teo

IPC: H01L21/768

Abstract: Electronic devices and methods of forming electronic devices using a reduced number of hardmask materials and reusing lithography reticles are described. Patterned substrates are formed using a combination of etch selective hardmask materials and reusing reticles to provide a pattern of repeating trapezoidal and rhomboidal openings.

公开(公告)号：US11846836B2

公开(公告)日：2023-12-19

申请号：US17306853

申请日：2021-05-03

Applicant: Applied Materials, Inc.

Inventor： Russell Chin Yee Teo ,  Ludovic Godet ,  Nir Yahav ,  Robert Jan Visser

IPC: G02F1/035 ,  C30B1/02 ,  C30B29/32

CPC classification number: G02F1/035 ,  C30B1/02 ,  C30B29/32

Abstract: An electro-optical waveguide modulator device includes a seed layer on a substrate, the seed layer having a first crystallographic plane aligned with a surface of the seed layer, an electro-optical channel extending in a first direction on the seed layer and having a second crystallographic plane aligned with the surface of the seed layer, an insulator layer on both sides of the electro-optical channel on the substrate in a second direction perpendicular to the first direction, an electrode barrier layer on the electro-optical channel and the insulator layer, and one or more of electrodes extending in the second direction. The seed layer and the insulator layer each comprise material having a refractive index that is lower than the electro-optical channel.

公开(公告)号：US11302699B2

公开(公告)日：2022-04-12

申请号：US16868933

申请日：2020-05-07

Applicant: Applied Materials, Inc.

Inventor： Russell Chin Yee Teo

IPC: H01L21/768 ,  H01L27/108

Abstract: Electronic devices and methods of forming electronic devices using a reduced number of hardmask materials and reusing lithography reticles are described. Patterned substrates are formed using a combination of etch selective hardmask materials and reusing reticles to provide a pattern of repeating trapezoidal and rhomboidal openings.

公开(公告)号：US20220189965A1

公开(公告)日：2022-06-16

申请号：US17686850

申请日：2022-03-04

Applicant: Applied Materials, Inc.

Inventor： Russell Chin Yee Teo

IPC: H01L27/108 ,  H01L21/768

Abstract: Electronic devices and methods of forming electronic devices using a reduced number of hardmask materials and reusing lithography reticles are described. Patterned substrates are formed using a combination of etch selective hardmask materials and reusing reticles to provide a pattern of repeating trapezoidal and rhomboidal openings.

公开(公告)号：US20200373309A1

公开(公告)日：2020-11-26

申请号：US16868933

申请日：2020-05-07

Applicant: Applied Materials, Inc.

Inventor： Russell Chin Yee Teo

IPC: H01L27/108 ,  H01L21/768

Abstract: Electronic devices and methods of forming electronic devices using a reduced number of hardmask materials and reusing lithography reticles are described. Patterned substrates are formed using a combination of etch selective hardmask materials and reusing reticles to provide a pattern of repeating trapezoidal and rhomboidal openings.

公开(公告)号：US20210320106A1

公开(公告)日：2021-10-14

申请号：US17209677

申请日：2021-03-23

Applicant: Applied Materials, Inc.

Inventor： Russell Chin Yee Teo

IPC: H01L27/108 ,  G11C5/06

Abstract: Memory devices and methods of forming memory devices are described. Specifically, dynamic random-access memory (DRAM) devices are provided with a capacitor landing pad able to connect a 6f2 layout to a 4f2 layout. In some embodiments, the capacitor landing pad has a plurality of air gaps.

公开(公告)号：US11024746B2

公开(公告)日：2021-06-01

申请号：US16818259

申请日：2020-03-13

Applicant: Applied Materials, Inc.

Inventor： Russell Chin Yee Teo ,  Benjamin Colombeau

IPC: H01L29/786 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/822

Abstract: Gate all-around devices are disclosed in which an angled channel comprising a semiconducting nanostructure is located between a source and a drain. The angled channel has an axis that is oriented at an angle to the top surface of the substrate at an angle in a range of about 1° to less than about 90°. The gate all-around device is intended to meet design and performance criteria for the 7 nm technology generation.

公开(公告)号：US20220020599A1

公开(公告)日：2022-01-20

申请号：US17378720

申请日：2021-07-18

Applicant: Applied Materials, Inc.

Inventor： Takehito Koshizawa ,  Karthik Janakiraman ,  Rui Cheng ,  Krishna Nittala ,  Menghui Li ,  Ming-Yuan Chuang ,  Susumu Shinohara ,  Juan Guo ,  Xiawan Yang ,  Russell Chin Yee Teo ,  Zihui Li ,  Chia-Ling Kao ,  Qu Jin ,  Anchuan Wang

IPC: H01L21/311 ,  H01L21/033 ,  H01J37/32

Abstract: Exemplary processing methods may include depositing a boron-containing material or a silicon-and-boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The methods may include etching portions of the boron-containing material or the silicon-and-boron-containing material with a chlorine-containing precursor to form one or more features in the substrate. The methods may also include removing remaining portions of the boron-containing material or the silicon-and-boron-containing material from the substrate with a fluorine-containing precursor.

公开(公告)号：US11133152B2

公开(公告)日：2021-09-28

申请号：US16711005

申请日：2019-12-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Regina Freed ,  Russell Chin Yee Teo ,  Madhur Sachan

IPC: H01J37/28 ,  G01B15/00

Abstract: Methods and apparatus for inspecting features on a substrate including exposing at least a portion of the substrate to a first electron beam landing energy to obtain a first image; exposing the at least a portion of the substrate to a second electron beam landing energy to obtain a second image, wherein the second electron beam landing energy is different from the first electron beam landing energy; realigning the first image and the second image to a feature on the substrate; and determining from at least one measurement from the first image associated with the feature and at least one measurement from the second image associated with the feature if the feature is leaning or twisting.

公开(公告)号：US20200220026A1

公开(公告)日：2020-07-09

申请号：US16818259

申请日：2020-03-13

Applicant: Applied Materials, Inc.

Inventor： Russell Chin Yee Teo ,  Benjamin Colombeau

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49 ,  H01L27/06 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L21/822

Abstract: Gate all-around devices are disclosed in which an angled channel comprising a semiconducting nanostructure is located between a source and a drain. The angled channel has an axis that is oriented at an angle to the top surface of the substrate at an angle in a range of about 1° to less than about 90°. The gate all-around device is intended to meet design and performance criteria for the 7 nm technology generation.