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公开(公告)号:US20210066064A1
公开(公告)日:2021-03-04
申请号:US17004850
申请日:2020-08-27
Applicant: APPLIED MATERIALS, INC.
Inventor: He REN , Shi YOU , Hao JIANG , Raymond HUNG , Mehul NAIK , Chentsau Chris YING , Mang-Mang LING , Lin DONG
IPC: H01L21/02
Abstract: Methods and apparatus for cleaning a contaminated metal surface on a substrate, including: exposing a substrate including a dielectric surface and a metal surface including metal nitride residues and metal carbide residues to a process gas including an oxidizing agent to form a substrate including a dielectric surface and a metal surface including metal oxides residues; and exposing a substrate including a dielectric surface and a metal surface including metal oxides residues to a process gas including a reducing agent to form a substrate including a dielectric surface and a substantially pure metal surface.
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公开(公告)号:US20150140827A1
公开(公告)日:2015-05-21
申请号:US14541978
申请日:2014-11-14
Applicant: Applied Materials, Inc.
Inventor: Chia-Ling KAO , Sean KANG , Jeremiah T. PENDER , Srinivas D. NEMANI , He REN , Mehul NAIK
IPC: H01L21/02 , H01L21/311
CPC classification number: H01L21/31116 , H01J37/32449 , H01J37/32477 , H01J37/32834 , H01J37/32871 , H01L21/02063 , H01L21/76802 , H01L21/76807 , H01L21/76826 , H01L21/76829
Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to methods for etching a low-k dielectric barrier layer disposed on a substrate using a non-carbon based approach. In one implementation, a method for etching a barrier low-k layer is provided. The method comprises (a) exposing a surface of the low-k barrier layer to a treatment gas mixture to modify at least a portion of the low-k barrier layer and (b) chemically etching the modified portion of the low-k barrier layer by exposing the modified portion to a chemical etching gas mixture, wherein the chemical etching gas mixture includes at least an ammonium gas and a nitrogen trifluoride gas or at least a hydrogen gas and a nitrogen trifluoride gas.
Abstract translation: 本文描述的实施方式通常涉及半导体制造,更具体地涉及使用非碳基方法蚀刻设置在基板上的低k电介质阻挡层的方法。 在一个实施方案中,提供了用于蚀刻阻挡层低k层的方法。 该方法包括(a)将低k阻挡层的表面暴露于处理气体混合物以修饰低k阻挡层的至少一部分,和(b)化学蚀刻低k阻挡层的修饰部分 通过将改性部分暴露于化学蚀刻气体混合物,其中化学蚀刻气体混合物至少包含铵气体和三氟化氮气体,或至少包含氢气和三氟化氮气体。
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公开(公告)号:US20250157851A1
公开(公告)日:2025-05-15
申请号:US18835577
申请日:2023-02-13
Applicant: Applied Materials, Inc.
Inventor: He REN , Houssam LAZKANI , Raman GAIRE , Mehul NAIK , Kuan-Ting LIU
IPC: H01L21/74 , H01L21/02 , H01L23/528 , H01L23/535
Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 seem to approximately 90 seem in a chamber pressure of approximately 1 Torr to approximately 100 Torr.
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公开(公告)号:US20220359224A1
公开(公告)日:2022-11-10
申请号:US17307383
申请日:2021-05-04
Applicant: Applied Materials, Inc.
Inventor: Hao JIANG , Chi LU , He REN , Mehul NAIK
IPC: H01L21/3213 , H01L21/033 , H01L21/67 , H01J37/32
Abstract: Methods and apparatus for processing a substrate are provided. For example, a method of processing a substrate comprises supplying oxygen (O2) into a processing volume of an etch chamber to react with a silicon-based hardmask layer atop a base layer of ruthenium to form a covering of an SiO-like material over the silicon-based hardmask layer and etching the base layer of ruthenium using at least one of O2 or chloride (Cl2) while supplying nitrogen (N2) to sputter some of the SiO-like material onto an exposed ruthenium sidewall created during etching.
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公开(公告)号:US20240379420A1
公开(公告)日:2024-11-14
申请号:US18781633
申请日:2024-07-23
Applicant: APPLIED MATERIALS, INC.
Inventor: Shi YOU , He REN , Naomi YOSHIDA , Nikolaos BEKIARIS , Mehul NAIK , Martin Jay SEAMONS , Jingmei LIANG , Mei-Yee SHEK
IPC: H01L21/768 , H01L21/02 , H01L21/67
Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material
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公开(公告)号:US20230260825A1
公开(公告)日:2023-08-17
申请号:US17670777
申请日:2022-02-14
Applicant: Applied Materials, Inc.
Inventor: He REN , Houssam LAZKANI , Raman GAIRE , Mehul NAIK , Kuan-Ting LIU
IPC: H01L21/74 , H01L23/528 , H01L21/20 , H01L23/535 , H01L21/02
CPC classification number: H01L21/743 , H01L23/5286 , H01L21/2022 , H01L23/535 , H01L21/02016
Abstract: A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.
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公开(公告)号:US20210317580A1
公开(公告)日:2021-10-14
申请号:US16848784
申请日:2020-04-14
Applicant: APPLIED MATERIALS, INC.
Inventor: Shi YOU , He REN , Naomi YOSHIDA , Nikolaos BEKIARIS , Mehul NAIK , Martin Jay SEAMONS , Jingmei LIANG , Mei-Yee SHEK
IPC: C23C16/56 , H01L21/768
Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material
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8.
公开(公告)号:US20190027403A1
公开(公告)日:2019-01-24
申请号:US16140342
申请日:2018-09-24
Applicant: APPLIED MATERIALS, INC.
Inventor: Sree Rangasai V. KESAPRAGADA , Kevin MORAES , Srinivas GUGGILLA , He REN , Mehul NAIK , David THOMPSON , Weifeng YE , Yana CHENG , Yong CAO , Xianmin TANG , Paul F. MA , Deenesh PADHI
IPC: H01L21/768 , H01L21/02
CPC classification number: H01L21/76832 , H01L21/02126 , H01L21/02167 , H01L21/02178 , H01L21/02211 , H01L21/02219 , H01L21/02266 , H01L21/02274 , H01L21/0228 , H01L21/3105 , H01L21/32 , H01L21/76826 , H01L21/76829 , H01L21/76834
Abstract: In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.
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9.
公开(公告)号:US20150140805A1
公开(公告)日:2015-05-21
申请号:US14523302
申请日:2014-10-24
Applicant: APPLIED MATERIALS, INC.
Inventor: Suketu A. PARIKH , Mehul NAIK
IPC: H01L21/768
CPC classification number: H01L21/76802 , H01L21/7682 , H01L21/7684 , H01L2221/1047
Abstract: Embodiments of methods for forming interconnect patterns on a substrate are provided herein. In some embodiments, a method for forming an interconnect pattern atop a substrate includes depositing a porous dielectric layer atop a cap layer and a plurality of spacers disposed atop the cap layer, wherein the cap layer is disposed atop a bulk dielectric layer and the bulk dielectric layer is disposed atop a substrate; removing a portion of the porous dielectric layer; removing the plurality of spacers to form features in the porous dielectric layer; and etching the cap layer to extend the features through the cap layer.
Abstract translation: 本文提供了在衬底上形成互连图案的方法的实施例。 在一些实施例中,用于在衬底顶部形成互连图案的方法包括在顶盖顶部沉积多孔电介质层,以及设置在顶盖顶部的多个间隔物,其中盖层设置在体电介质层的顶部, 层设置在基板的顶部; 去除所述多孔介电层的一部分; 去除所述多个间隔物以在所述多孔介电层中形成特征; 并且蚀刻所述盖层以通过所述盖层延伸所述特征。
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公开(公告)号:US20230187276A1
公开(公告)日:2023-06-15
申请号:US18108338
申请日:2023-02-10
Applicant: APPLIED MATERIALS, INC.
Inventor: Shi YOU , He REN , Naomi YOSHIDA , Nikolaos BEKIARIS , Mehul NAIK , Jay Martin SEAMONS , Jingmei LIANG , Mei-Yee SHEK
IPC: H01L21/768 , H01L21/02 , H01L21/67
CPC classification number: H01L21/76837 , H01L21/76828 , H01L21/76826 , H01L21/02337 , H01L21/76825 , H01L21/02323 , H01L21/76834 , H01L21/67103 , H01L21/02326
Abstract: Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material
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