公开(公告)号：US20140159234A1

公开(公告)日：2014-06-12

申请号：US13743450

申请日：2013-01-17

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Kai-Yi Wang

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/562 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/014

Abstract: A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.

Abstract translation: 半导体制造方法包括以下步骤：提供具有至少一个连接焊盘和保护层的硅衬底，形成具有至少一个第一部分和至少一个第二部分的第一种子层，形成第一光致抗蚀剂层，形成第 第一缓冲层，具有耦合部分和包层部分，去除第一光致抗蚀剂层，去除第一种子层的第二部分以形成第一凸块下金属层，在保护层和第一缓冲层上形成支撑层， 所述第一凸块下金属层具有第一环壁，所述第一缓冲层具有第二环壁，所述第一环壁，所述第二环壁和所述包层部由所述支撑层包覆，并且形成连接部和覆盖层 与连接部分的联接部分。

公开(公告)号：US20160020166A1

公开(公告)日：2016-01-21

申请号：US14515719

申请日：2014-10-16

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yung-Wei Hsieh ,  Cheng-Hung Shih ,  Kai-Yi Wang ,  Heh-Chang Huang ,  Po-Hao Chen

IPC: H01L23/50

CPC classification number: H01L23/49838 ,  H01L21/4846

Abstract: A trace structure of fine-pitch pattern includes a connection portion, a first conductive wire portion and a second conductive wire portion, the first conductive wire portion comprises a first section and a second section connected to the first section, the first section connects to the connection portion, the second conductive wire portion comprises a third section and a fourth section connected to the third section, the third section connects to the connection portion, wherein an etching space closed on three sides is formed by the connection portion, the third section and the first section, a first spacing is defined between the third section and the first section, a second spacing is defined between the fourth section and the second section, wherein the first spacing is larger than the second spacing so as to make an metal layer within the etching space completely removed to avoid metal layer residues.

Abstract translation: 细间距图案的迹线结构包括连接部分，第一导线部分和第二导线部分，第一导线部分包括连接到第一部分的第一部分和第二部分，第一部分连接到 连接部分，第二导线部分包括连接到第三部分的第三部分和第四部分，第三部分连接到连接部分，其中通过连接部分，第三部分和第三部分形成三面封闭的蚀刻空间， 所述第一部分在所述第三部分和所述第一部分之间限定第一间隔，在所述第四部分和所述第二部分之间限定第二间隔，其中所述第一间隔大于所述第二间隔，以使所述第一部分内的金属层在 蚀刻空间完全去除以避免金属层残留。

公开(公告)号：US08877629B2

公开(公告)日：2014-11-04

申请号：US13743450

申请日：2013-01-17

Applicant: Chipbond Technology Corporation

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Kai-Yi Wang

IPC: H01L21/44 ,  H01L23/498 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/014

Abstract: A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.

Abstract translation: 半导体制造方法包括以下步骤：提供具有至少一个连接焊盘和保护层的硅衬底，形成具有至少一个第一部分和至少一个第二部分的第一种子层，形成第一光致抗蚀剂层，形成第 第一缓冲层，具有耦合部分和包层部分，去除第一光致抗蚀剂层，去除第一种子层的第二部分以形成第一凸块下金属层，在保护层和第一缓冲层上形成支撑层， 所述第一凸块下金属层具有第一环壁，所述第一缓冲层具有第二环壁，所述第一环壁，所述第二环壁和所述包层部由所述支撑层包覆，并且形成连接部和覆盖层 与连接部分的联接部分。

公开(公告)号：US20140367856A1

公开(公告)日：2014-12-18

申请号：US14474558

申请日：2014-09-02

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Kai-Yi Wang

IPC: H01L23/00 ,  H01L23/48

CPC classification number: H01L23/562 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/014

Abstract: A semiconductor manufacturing process includes the following steps of providing a silicon substrate having at least one connection pad and a protection layer, forming a first seed layer having at least one first section and at least one second section, forming a first photoresist layer, forming a first buffer layer having a coupling portion and a cladding portion, removing the first photoresist layer, removing the second section of the first seed layer to form a first under bump metallurgy layer, forming a support layer on the protection layer and the first buffer layer, the first under bump metallurgy layer has a first ring wall, the first buffer layer has a second ring wall, wherein the first ring wall, the second ring wall and the cladding portion are cladded by the support layer, and forming a connection portion and covering the coupling portion with the connection portion.