公开(公告)号：US20180286491A1

公开(公告)日：2018-10-04

申请号：US15478666

申请日：2017-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor ARSOVSKI ,  Eric D. HUNT-SCHROEDER ,  Michael A. ZIEGERHOFER

IPC: G11C29/12 ,  G06F12/1027 ,  G06F12/0806 ,  G06F12/1009

CPC classification number: G11C29/12 ,  G06F12/1027 ,  G06F2212/65 ,  G06F2212/68 ,  G11C8/16 ,  G11C2029/0409

Abstract: The present disclosure relates to a structure which includes a memory which is configured to enable zero test time built-in self-test (BIST) at a read/write port while concurrently performing at least one functional read operation at a read port.

公开(公告)号：US20160172038A1

公开(公告)日：2016-06-16

申请号：US15048256

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor ARSOVSKI

IPC: G11C15/04 ,  G11C11/417

CPC classification number: G11C15/046 ,  G06F11/1064 ,  G06F17/30982 ,  G11C11/417 ,  G11C15/04 ,  H04L45/7457

Abstract: Approaches for an integrated circuit ternary content addressable memory (TCAM) are provided. A system includes an array of XY TCAM cells and respective translation circuits connected to respective pairs of the XY TCAM cells. The system also includes a memory controller structured to provide control signals to the respective translation circuits. The memory controller and respective translation circuits are structured to control the array of XY TCAM cells to perform single cycle update and single cycle search operations.

公开(公告)号：US20180108642A1

公开(公告)日：2018-04-19

申请号：US15292552

申请日：2016-10-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wolfgang SAUTER ,  Igor ARSOVSKI

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/34 ,  G11C5/02

CPC classification number: H01L25/18 ,  G11C5/02 ,  H01L23/147 ,  H01L23/345 ,  H01L25/50

Abstract: A method for integrating heaters in high bandwidth memory (HBM) applications and the related devices are provided. Embodiments include forming a silicon (Si) interposer over a substrate; forming HBM and an integrated circuit (IC) over the Si interposer; forming a heater on the Si interposer in a space between the HBM and Si interposer; and utilizing one or more temperature sensors in the HBM to monitor a temperature of the HBM.

公开(公告)号：US20210082532A1

公开(公告)日：2021-03-18

申请号：US16568394

申请日：2019-09-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Eric D. HUNT-SCHROEDER ,  Sebastian T. VENTRONE ,  James A. SVARCZKOPF ,  Igor ARSOVSKI

IPC: G11C17/18

Abstract: The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.

公开(公告)号：US20170352407A1

公开(公告)日：2017-12-07

申请号：US15175466

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor ARSOVSKI ,  Qing LI ,  Wei ZHAO ,  Xiaoli HU

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/067

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sensing circuit for a memory and methods of use. The memory includes a self-referenced sense amp that is structured to calibrate its individual pre-charge based on a trip-point, with autonomous pre-charge activation circuitry that starts pre-charging a sense-line on each unique entry as soon as a sense has been performed or completed.

公开(公告)号：US20190295676A1

公开(公告)日：2019-09-26

申请号：US15928587

申请日：2018-03-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor ARSOVSKI ,  Kyle M. HOLMES

IPC: G11C29/12 ,  G11C29/50

Abstract: The present disclosure relates to a device including a built-in-self-test (BIST) circuit configured to run a BIST pattern in a loop mode on a memory which is customized for activity factors corresponding to a programmable number of operations, the BIST circuit being further configured to measure dynamic power on a supply while running the BIST pattern in the loop mode on the memory.

公开(公告)号：US20190066786A1

公开(公告)日：2019-02-28

申请号：US15684492

申请日：2017-08-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Igor ARSOVSKI ,  Qing LI ,  Xiaoli HU ,  Wei ZHAO ,  Jieyao LIU

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C7/065 ,  G11C7/12 ,  G11C11/419 ,  G11C2207/002

Abstract: The present disclosure relates to a structure which includes a self-referenced multiplexer circuit which is configured to pre-charge a plurality of sense lines to a voltage threshold in a first time period and sense and detect a value of a selected sense line of the sense lines in a second time period.