公开(公告)号：US20250159905A1

公开(公告)日：2025-05-15

申请号：US18509591

申请日：2023-11-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Halid Mulaosmanovic ,  Peter Baars

IPC: H10B63/00 ,  H01L23/48 ,  H10B63/10 ,  H10N70/00

Abstract: Structures that include a switching memory element and methods of forming a structure including a switching memory element. The structure comprises a switching memory element, and a two-terminal access device including a first terminal coupled to the switching memory element, a second terminal, and a semiconductor layer between the first terminal and the second terminal. The semiconductor layer is electrically floating in the structure.

公开(公告)号：US12176023B2

公开(公告)日：2024-12-24

申请号：US18080456

申请日：2022-12-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pirooz Parvarandeh ,  Venkatesh P. Gopinath ,  Navneet Jain ,  Bipul C. Paul ,  Halid Mulaosmanovic

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419 ,  H01L21/28 ,  H10B10/00

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.

公开(公告)号：US20240194253A1

公开(公告)日：2024-06-13

申请号：US18080456

申请日：2022-12-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Pirooz Parvarandeh ,  Venkatesh P. Gopinath ,  Navneet Jain ,  Bipul C. Paul ,  Halid Mulaosmanovic

IPC: G11C11/412 ,  G11C11/419 ,  H01L21/28 ,  H10B10/00

CPC classification number: G11C11/412 ,  G11C11/419 ,  H01L27/1104 ,  H01L29/40111

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure comprises a static random access memory bit cell including a first node and a second node, a first ferroelectric field-effect transistor including a first terminal connected to the first node, and a second ferroelectric field-effect transistor including a second terminal connected to the second node.