公开(公告)号：US20170125352A1

公开(公告)日：2017-05-04

申请号：US15352405

申请日：2016-11-15

Applicant: Honeywell International Inc.

Inventor： Eric E. Vogt ,  Gregor D. Dougal ,  James L. Tucker

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L23/13 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L23/57 ,  H01L23/573 ,  H01L24/05 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/83805 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.

公开(公告)号：US20140332922A1

公开(公告)日：2014-11-13

申请号：US13891280

申请日：2013-05-10

Applicant: HONEYWELL INTERNATIONAL INC.

Inventor： Eric E. Vogt ,  Paul S. Fechner ,  Gordon A. Shaw

IPC: H01L23/525 ,  H01L21/768

CPC classification number: H01L23/5256 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some examples, a programmable electrical fuse includes at least one structural feature that increases a thermal gradient between an anode and a cathode of the programmable electrical fuse. For example, a device may include a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and a programmable electrical fuse overlying a portion of the electrically insulating layer. The programmable electrical fuse may include a cathode, an anode, and a conductor link connecting the cathode and the anode. The electrically insulating layer may define a first thickness between the semiconductor substrate and the cathode and a second thickness between the semiconductor substrate and the anode, and the first thickness being less than the second thickness.

Abstract translation: 在一些示例中，可编程电熔丝包括增加可编程电熔丝的阳极和阴极之间的热梯度的至少一个结构特征。 例如，器件可以包括半导体衬底，覆盖半导体衬底的电绝缘层和覆盖电绝缘层的一部分的可编程电熔丝。 可编程电熔丝可以包括阴极，阳极和连接阴极和阳极的导体连接。 电绝缘层可以限定半导体衬底和阴极之间的第一厚度以及半导体衬底和阳极之间的第二厚度，并且第一厚度小于第二厚度。

公开(公告)号：US09548277B2

公开(公告)日：2017-01-17

申请号：US14692154

申请日：2015-04-21

Applicant: Honeywell International Inc.

Inventor： Eric E. Vogt ,  Gregor D. Dougal ,  James L. Tucker

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/28 ,  H01L21/56 ,  H01L25/00 ,  H01L23/498

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L23/13 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L23/57 ,  H01L23/573 ,  H01L24/05 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/83805 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.

Abstract translation: 本公开描述了一种堆叠集成电路系统，其包括堆叠在插入层的相对侧上的两个集成电路层。 插入层可以包括至少一个集成电路管芯和内插器部分，其包括布置在插入层内的横向图案化阵列中的多个导电柱。

公开(公告)号：US20160315055A1

公开(公告)日：2016-10-27

申请号：US14692154

申请日：2015-04-21

Applicant: Honeywell International Inc.

Inventor： Eric E. Vogt ,  Gregor D. Dougal ,  James L. Tucker

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L23/28 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L23/13 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L23/57 ,  H01L23/573 ,  H01L24/05 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/83805 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.

Abstract translation: 本公开描述了一种堆叠集成电路系统，其包括堆叠在插入层的相对侧上的两个集成电路层。 插入层可以包括至少一个集成电路管芯和内插器部分，其包括布置在插入层内的横向图案化阵列中的多个导电柱。

公开(公告)号：US09997466B2

公开(公告)日：2018-06-12

申请号：US15352405

申请日：2016-11-15

Applicant: Honeywell International Inc.

Inventor： Eric E. Vogt ,  Gregor D. Dougal ,  James L. Tucker

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L23/13 ,  H01L23/28 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/552 ,  H01L23/57 ,  H01L23/573 ,  H01L24/05 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/83805 ,  H01L2225/06513 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: The present disclosure describes a stacked integrated circuit system that includes two integrated circuit layers stacked on opposite sides of an interposer layer. The interposer layer may include at least one integrated circuit die and an interposer portion that includes a plurality of electrically conductive pillars arranged in a laterally patterned array within the interposer layer.

公开(公告)号：US20240347386A1

公开(公告)日：2024-10-17

申请号：US18299368

申请日：2023-04-12

Applicant: Honeywell International Inc.

Inventor： James L. Tucker ,  Eric E. Vogt ,  James W, Karcz, JR.

IPC: H01L21/822 ,  H01L23/373 ,  H01L23/50

CPC classification number: H01L21/8221 ,  H01L23/3733 ,  H01L23/50 ,  H01L2021/60097 ,  H01L2021/60225

Abstract: A semiconductor assembly including: a first semiconductor having a plurality of electrical contacts extending from an upper surface of the first semiconductor; a second semiconductor adjacent to the first semiconductor; and a mesh disposed between and affixed to the upper surface of the first semiconductor and the lower surface of the second semiconductor. A lower surface of the second semiconductor is electrically connected to the first semiconductor via the plurality of electrical contacts. The mesh comprises a plurality of interconnecting struts defining a plurality of openings, wherein the plurality of openings is configured to receive the plurality of electrical contacts.

公开(公告)号：US08901702B1

公开(公告)日：2014-12-02

申请号：US13891280

申请日：2013-05-10

Applicant: Honeywell International Inc.

Inventor： Eric E. Vogt ,  Paul S. Fechner ,  Gordon A. Shaw

IPC: H01L29/00 ,  H01L21/768 ,  H01L23/525

CPC classification number: H01L23/5256 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some examples, a programmable electrical fuse includes at least one structural feature that increases a thermal gradient between an anode and a cathode of the programmable electrical fuse. For example, a device may include a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and a programmable electrical fuse overlying a portion of the electrically insulating layer. The programmable electrical fuse may include a cathode, an anode, and a conductor link connecting the cathode and the anode. The electrically insulating layer may define a first thickness between the semiconductor substrate and the cathode and a second thickness between the semiconductor substrate and the anode, and the first thickness being less than the second thickness.

Abstract translation: 在一些示例中，可编程电熔丝包括增加可编程电熔丝的阳极和阴极之间的热梯度的至少一个结构特征。 例如，器件可以包括半导体衬底，覆盖半导体衬底的电绝缘层和覆盖电绝缘层的一部分的可编程电熔丝。 可编程电熔丝可以包括阴极，阳极和连接阴极和阳极的导体连接。 电绝缘层可以限定半导体衬底和阴极之间的第一厚度以及半导体衬底和阳极之间的第二厚度，并且第一厚度小于第二厚度。