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    pH sensor with substrate or bonding layer configured to maintain piezoresistance of the ISFET die
    2.
    发明授权
    pH sensor with substrate or bonding layer configured to maintain piezoresistance of the ISFET die 有权

    公开(公告)号：US09664641B2

    公开(公告)日：2017-05-30

    申请号：US13952888

    申请日：2013-07-29

    Applicant: Honeywell International Inc.

    Inventor： Donald Horkheimer ,  Paul S. Fechner ,  David S. Willits

    IPC: G01N27/414 ,  G01N27/416

    CPC classification number: G01N27/414 ,  G01N27/4167

    Abstract: Embodiments described herein provide for a pH sensor that is configured for use over a pressure and temperature range. The ISFET die of the pH sensor is bonded to the substrate of the pH sensor with a bonding layer that is disposed between the substrate and the ISFET die. The pressure and temperature change across the pressure and temperature range generates an environmental force in the pH sensor. Further, the substrate or the bonding layer or both change volume over the pressure and temperature range, and the substrate or the bonding layer or both are configured such that the volume change induces a counteracting force that opposes at least a portion of the environmental force. The counteracting force is configured to maintain the change in piezoresistance of the ISFET die from the drain to the source to less than 0.5% over the pressure and temperature range.

    pH SENSOR WITH SUBSTRATE OR BONDING LAYER CONFIGURED TO MAINTAIN PIEZORESISTANCE OF THE ISFET DIE
    3.
    发明申请
    pH SENSOR WITH SUBSTRATE OR BONDING LAYER CONFIGURED TO MAINTAIN PIEZORESISTANCE OF THE ISFET DIE 有权
    具有基板或粘结层的pH传感器配置为维持ISFET DIE的绝缘

    公开(公告)号：US20150028396A1

    公开(公告)日：2015-01-29

    申请号：US13952888

    申请日：2013-07-29

    Applicant: Honeywell International Inc.

    Inventor： Donald Horkheimer ,  Paul S. Fechner ,  David S. Willits

    IPC: G01N27/414 ,  G01N27/416

    CPC classification number: G01N27/414 ,  G01N27/4167

    Abstract: Embodiments described herein provide for a pH sensor that is configured for use over a pressure and temperature range. The ISFET die of the pH sensor is bonded to the substrate of the pH sensor with a bonding layer that is disposed between the substrate and the ISFET die. The pressure and temperature change across the pressure and temperature range generates an environmental force in the pH sensor. Further, the substrate or the bonding layer or both change volume over the pressure and temperature range, and the substrate or the bonding layer or both are configured such that the volume change induces a counteracting force that opposes at least a portion of the environmental force. The counteracting force is configured to maintain the change in piezoresistance of the ISFET die from the drain to the source to less than 0.5% over the pressure and temperature range.

    Abstract translation: 本文所述的实施例提供了一种配置成在压力和温度范围内使用的pH传感器。 pH传感器的ISFET管芯通过设置在基板和ISFET管芯之间的接合层与pH传感器的基板结合。 在压力和温度范围内的压力和温度变化在pH传感器中产生环境力。 此外，衬底或接合层或两者都在压力和温度范围内改变体积，并且衬底或接合层或两者被配置为使得体积变化引起与至少一部分环境力相反的抵抗力。 反作用力被配置为在压力和温度范围内保持ISFET管芯从漏极到源极的压阻变化小于0.5％。

    pH SENSOR WITH BONDING AGENT DISPOSED IN A PATTERN
    5.
    发明申请
    pH SENSOR WITH BONDING AGENT DISPOSED IN A PATTERN 有权
    带有粘结剂的pH传感器在图案中处理

    公开(公告)号：US20150028395A1

    公开(公告)日：2015-01-29

    申请号：US13952879

    申请日：2013-07-29

    Applicant: Honeywell International Inc.

    Inventor： Donald Horkheimer ,  Paul S. Fechner ,  David S. Willits

    IPC: G01N27/414 ,  H01L23/00 ,  C03C27/00 ,  B32B37/12

    CPC classification number: G01N27/414 ,  B32B37/1292 ,  C03C27/00 ,  G01N27/4148 ,  H01L24/33 ,  H01L24/83 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/35 ,  H01L2924/00

    Abstract: Embodiments described herein provide for a pH sensor that comprises a substrate and an ion sensitive field effect transistor (ISFET) die. The ISFET die includes an ion sensing part that is configured to be exposed to a medium such that it outputs a signal related to the pH level of the medium. The ISFET die is bonded to the substrate with at least one composition of bonding agent material disposed between the ISFET die and the substrate. One or more strips of the at least one composition of bonding agent material is disposed between the substrate and the ISFET die in a first pattern.

    Abstract translation: 本文所述的实施例提供了一种pH传感器，其包括基板和离子敏感场效应晶体管（ISFET）管芯。 ISFET管芯包括被配置为暴露于介质的离子感测部件，使得其输出与介质的pH水平相关的信号。 ISFET管芯通过至少一种配置在ISFET管芯和衬底之间的粘合剂材料的组合物结合到衬底上。 粘合剂材料的至少一种组合物的一个或多个条以第一图案设置在基板和ISFET管芯之间。

    Converter for analog inputs
    6.
    发明授权
    Converter for analog inputs 有权
    模拟输入转换器

    公开(公告)号：US09246501B2

    公开(公告)日：2016-01-26

    申请号：US14265040

    申请日：2014-04-29

    Applicant: Honeywell International Inc.

    Inventor： James L. Tucker ,  Paul S. Fechner

    IPC: H03M1/60 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12

    CPC classification number: H03M1/002 ,  H03M1/0619 ,  H03M1/0621 ,  H03M1/122 ,  H03M1/60

    Abstract: A device having a first oscillator circuit configured to generate a first signal with a first frequency based on an analog input and external characteristics, and a second oscillator circuit configured to generate a second signal with a second frequency based on a constant voltage and the external characteristics. The device also having one or more discrete logic gates configured to generate a digital composite signal based on the first signal and the second signal, such that a number of transitions in the digital composite signal over a period of time, based on the first frequency of the first signal, are indicative of the analog input.

    Abstract translation: 一种具有第一振荡器电路的装置，被配置为基于模拟输入和外部特性产生具有第一频率的第一信号，以及第二振荡器电路，被配置为基于恒定电压和外部特性产生具有第二频率的第二信号 。 该装置还具有一个或多个离散逻辑门，其被配置为基于第一信号和第二信号产生数字复合信号，使得在一段时间内基于第一频率的第一频率的数字复合信号中的转换次数 第一个信号表示模拟输入。

    CONVERTER FOR ANALOG INPUTS
    7.
    发明申请
    CONVERTER FOR ANALOG INPUTS 有权
    模拟输入转换器

    公开(公告)号：US20150311909A1

    公开(公告)日：2015-10-29

    申请号：US14265040

    申请日：2014-04-29

    Applicant: HONEYWELL INTERNATIONAL INC.

    Inventor： James L. Tucker ,  Paul S. Fechner

    IPC: H03M1/00 ,  H03M1/12 ,  H03M1/06

    CPC classification number: H03M1/002 ,  H03M1/0619 ,  H03M1/0621 ,  H03M1/122 ,  H03M1/60

    Abstract: A device having a first oscillator circuit configured to generate a first signal with a first frequency based on an analog input and external characteristics, and a second oscillator circuit configured to generate a second signal with a second frequency based on a constant voltage and the external characteristics. The device also having one or more discrete logic gates configured to generate a digital composite signal based on the first signal and the second signal, such that a number of transitions in the digital composite signal over a period of time, based on the first frequency of the first signal, are indicative of the analog input.

    Abstract translation: 一种具有第一振荡器电路的装置，被配置为基于模拟输入和外部特性产生具有第一频率的第一信号，以及第二振荡器电路，被配置为基于恒定电压和外部特性产生具有第二频率的第二信号 。 该装置还具有一个或多个离散逻辑门，其被配置为基于第一信号和第二信号产生数字复合信号，使得在一段时间内基于第一频率的第一频率的数字复合信号中的转换次数 第一个信号表示模拟输入。

    CMOS logic circuit using passive internal body tie bias
    8.
    发明授权
    CMOS logic circuit using passive internal body tie bias 有权
    CMOS逻辑电路采用被动内部机身引线偏置

    公开(公告)号：US08975952B2

    公开(公告)日：2015-03-10

    申请号：US13675828

    申请日：2012-11-13

    Applicant: Honeywell International Inc.

    Inventor： Paul S. Fechner ,  Weston Roper ,  James D. Seefeldt

    IPC: H03K3/01 ,  H03K19/094

    CPC classification number: H03K19/09421 ,  H03K3/01

    Abstract: This disclosure is directed to devices, integrated circuits, systems, and methods for implementing an internal body tie bias circuit in a CMOS logic circuit. In one example, a CMOS logic circuit is formed in an integrated circuit. The CMOS logic circuit includes a PMOS transistor, an NMOS transistor; and a body tie bias circuit formed in the integrated circuit. The body tie bias circuit is coupled between a body tie connection terminal of the PMOS transistor and a body tie connection terminal of the NMOS transistor.

    Abstract translation: 本公开涉及用于在CMOS逻辑电路中实现内部主体偏置电路的装置，集成电路，系统和方法。 在一个示例中，CMOS逻辑电路形成在集成电路中。 CMOS逻辑电路包括PMOS晶体管，NMOS晶体管; 以及在集成电路中形成的主体偏置电路。 体引线偏置电路耦合在PMOS晶体管的主体连接端子和NMOS晶体管的主体连接端子之间。

    Programmable electrical fuse with temperature gradient between anode and cathode
    9.
    发明授权
    Programmable electrical fuse with temperature gradient between anode and cathode 有权
    可编程电气保险丝，阳极和阴极之间具有温度梯度

    公开(公告)号：US08901702B1

    公开(公告)日：2014-12-02

    申请号：US13891280

    申请日：2013-05-10

    Applicant: Honeywell International Inc.

    Inventor： Eric E. Vogt ,  Paul S. Fechner ,  Gordon A. Shaw

    IPC: H01L29/00 ,  H01L21/768 ,  H01L23/525

    CPC classification number: H01L23/5256 ,  H01L23/53271 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In some examples, a programmable electrical fuse includes at least one structural feature that increases a thermal gradient between an anode and a cathode of the programmable electrical fuse. For example, a device may include a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and a programmable electrical fuse overlying a portion of the electrically insulating layer. The programmable electrical fuse may include a cathode, an anode, and a conductor link connecting the cathode and the anode. The electrically insulating layer may define a first thickness between the semiconductor substrate and the cathode and a second thickness between the semiconductor substrate and the anode, and the first thickness being less than the second thickness.

    Abstract translation: 在一些示例中，可编程电熔丝包括增加可编程电熔丝的阳极和阴极之间的热梯度的至少一个结构特征。 例如，器件可以包括半导体衬底，覆盖半导体衬底的电绝缘层和覆盖电绝缘层的一部分的可编程电熔丝。 可编程电熔丝可以包括阴极，阳极和连接阴极和阳极的导体连接。 电绝缘层可以限定半导体衬底和阴极之间的第一厚度以及半导体衬底和阳极之间的第二厚度，并且第一厚度小于第二厚度。

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