公开(公告)号：US12242730B2

公开(公告)日：2025-03-04

申请号：US18190055

申请日：2023-03-24

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Yin Ping Gao ,  Qi-Ao Zhu ,  Kuai Cao ,  Dong Sheng Rao

IPC: G06F3/06

Abstract: A data arrangement method based on file system, a memory storage device and a memory control circuit unit are disclosed. The method includes: analyzing a file system stored in a system region to obtain a plurality of first logical units to which a first file belongs and first distribution information of a plurality of first physical units in a storage region, wherein the first physical units are mapped by the first logical units; determining whether to activate a data arrangement operation on the first file according to the first distribution information; after the data arrangement operation on the first file is activated, reading first data belonging to the first file from the first physical units; and writing, sequentially, the read first data to at least one second physical unit in the storage region.

公开(公告)号：US20240289017A1

公开(公告)日：2024-08-29

申请号：US18190147

申请日：2023-03-27

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Dong Dong Yao ,  Yun Peng Zhang ,  Kuai Cao ,  En Yang Wang ,  Wen Qing Lv

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0634 ,  G06F3/0679

Abstract: A performance match method of memory, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a performance match command from a host system; in response to the performance match command, adjusting an operation setting of a memory storage device to match a performance of the memory storage device with a performance requirement of the host system; and interacting with the host system based on the adjusted operation setting.

公开(公告)号：US12099753B2

公开(公告)日：2024-09-24

申请号：US18190152

申请日：2023-03-27

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Ya Jie Guo ,  En Yang Wang ,  Kuai Cao ,  Dong Dong Yao ,  Yun Peng Zhang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A mapping table updating method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving, a plurality of operation commands from a host system; performing a first table updating operation according to a first operation command and a third operation command among the operation commands to read and update a first sub-mapping table and a third sub-mapping table from a rewritable non-volatile memory module; and after the first table updating operation is finished, performing a second table updating operation according to a second operation command among the operation commands to read and update a second sub-mapping table from the rewritable non-volatile memory module.

公开(公告)号：US20240295982A1

公开(公告)日：2024-09-05

申请号：US18298345

申请日：2023-04-10

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Wan-Jun Hong ,  Qi-Ao Zhu ,  Yang Zhang ,  Xin Wang

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory operation control method, a memory storage device, and a memory control circuit unit are disclosed. The method includes the following. Management data is established, which includes status recording data. First status information corresponding to a first physical unit is stored in the status recording data. An operation command is received from a host system. The management data is queried according to the operation command. Whether to allow an execution of the operation command on the first physical unit is determined according to a query result.

公开(公告)号：US20240289051A1

公开(公告)日：2024-08-29

申请号：US18190152

申请日：2023-03-27

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Ya Jie Guo ,  En Yang Wang ,  Kuai Cao ,  Dong Dong Yao ,  Yun Peng Zhang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A mapping table updating method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving, a plurality of operation commands from a host system; performing a first table updating operation according to a first operation command and a third operation command among the operation commands to read and update a first sub-mapping table and a third sub-mapping table from a rewritable non-volatile memory module; and after the first table updating operation is finished, performing a second table updating operation according to a second operation command among the operation commands to read and update a second sub-mapping table from the rewritable non-volatile memory module.

公开(公告)号：US20230297232A1

公开(公告)日：2023-09-21

申请号：US17717168

申请日：2022-04-11

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Qi-Ao Zhu ,  Jing Zhang ,  Jian Hu

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0655 ,  G06F3/0679

Abstract: A table sorting method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to a first voltage management table among multiple voltage management tables; decoding the first data; in response to the first data being successfully decoded, updating count information corresponding to the first voltage management table; and in response to the count information meeting a default condition, increasing a usage priority of the first voltage management table among the voltage management tables.

公开(公告)号：US11715532B1

公开(公告)日：2023-08-01

申请号：US17833901

申请日：2022-06-07

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Yue Hu ,  Qin Qin Tao ,  Dong Sheng Rao ,  Shao Feng Yang ,  Yang Chen

IPC: G11C29/00 ,  G11C16/34 ,  G06F12/14

CPC classification number: G11C16/3422 ,  G06F12/1433 ,  G11C16/3431 ,  G11C29/00

Abstract: A risk assessment method based on data priority, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a query command from a host system; in response to the query command, performing a data health detection on a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module stores data with multiple data priorities; generating risk assessment information according to a detection result, wherein the risk assessment information reflects a health degree of data with different data priorities in the rewritable non-volatile memory modules by different risk levels; and transmitting the risk assessment information to the host system.

公开(公告)号：US20250123641A1

公开(公告)日：2025-04-17

申请号：US18504163

申请日：2023-11-08

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Qi-Ao Zhu ,  Dong Sheng Rao

IPC: G05D23/24 ,  G01K7/22

Abstract: A temperature control method and a temperature control system for controlling a temperature of a target device are disclosed. The target device is disposed in a temperature control device. The method includes: controlling an internal temperature of the temperature control device according to a base parameter and a compensation parameter; detecting a temperature of the target device via a temperature sensor during the period that the internal temperature of the temperature control device is controlled according to the base parameter and the compensation parameter; and adjusting the compensation parameter according to the temperature of the target device to change the internal temperature of the temperature control device.

公开(公告)号：US12147674B1

公开(公告)日：2024-11-19

申请号：US18761237

申请日：2024-07-01

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Dong Dong Yao ,  Kuai Cao

IPC: G06F3/06 ,  G11C29/12

Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: setting preset read count thresholds corresponding to physical erasing units respectively; in a background operation, in response to a read count of a first physical erasing unit in the physical erasing units being greater than its corresponding preset read count threshold, reading word lines in the first physical erasing unit to obtain first error bit amounts; determining whether a refresh operation needs to be performed on the first physical erasing unit according to first error bit amounts; in response to no need to perform the refresh operation on the first physical erasing unit, selecting a first word line with the largest first error bit amount in the word lines, and detecting a voltage distribution variation of the first word line; and calculating a new read count threshold of the first physical erasing unit according to the voltage distribution variation.

公开(公告)号：US20240289022A1

公开(公告)日：2024-08-29

申请号：US18190055

申请日：2023-03-24

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Yin Ping Gao ,  Qi-Ao Zhu ,  Kuai Cao ,  Dong Sheng Rao

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: A data arrangement method based on file system, a memory storage device and a memory control circuit unit are disclosed. The method includes: analyzing a file system stored in a system region to obtain a plurality of first logical units to which a first file belongs and first distribution information of a plurality of first physical units in a storage region, wherein the first physical units are mapped by the first logical units; determining whether to activate a data arrangement operation on the first file according to the first distribution information; after the data arrangement operation on the first file is activated, reading first data belonging to the first file from the first physical units; and writing, sequentially, the read first data to at least one second physical unit in the storage region.