公开(公告)号：US12147671B2

公开(公告)日：2024-11-19

申请号：US18190147

申请日：2023-03-27

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Dong Dong Yao ,  Yun Peng Zhang ,  Kuai Cao ,  En Yang Wang ,  Wen Qing Lv

IPC: G06F3/06

Abstract: A performance match method of memory, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a performance match command from a host system; in response to the performance match command, adjusting an operation setting of a memory storage device to match a performance of the memory storage device with a performance requirement of the host system; and interacting with the host system based on the adjusted operation setting.

公开(公告)号：US20230359357A1

公开(公告)日：2023-11-09

申请号：US17745891

申请日：2022-05-17

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  FAN YI ,  Kuai Cao ,  Yang Chen ,  Qin Qin Tao ,  Dong Sheng Rao

IPC: G06F3/06 ,  G06F11/07

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/073

Abstract: A write control method based on write behavior prediction, a memory storage device, and a memory control circuit unit are provided. The method includes: monitoring a first data write behavior of a host system during a first time range; according to the first data write behavior, predicting a second data write behavior of the host system during a second time range; obtaining a first measurement parameter and a first target parameter corresponding to the first data write behavior; according to the first measurement parameter, the first target parameter, and the second data write behavior, determining a write control parameter; and sending a write command sequence according to the write control parameter to instruct a rewritable non-volatile memory module to perform a data write based on multiple write modes during the second time range.

公开(公告)号：US12147674B1

公开(公告)日：2024-11-19

申请号：US18761237

申请日：2024-07-01

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Dong Dong Yao ,  Kuai Cao

IPC: G06F3/06 ,  G11C29/12

Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: setting preset read count thresholds corresponding to physical erasing units respectively; in a background operation, in response to a read count of a first physical erasing unit in the physical erasing units being greater than its corresponding preset read count threshold, reading word lines in the first physical erasing unit to obtain first error bit amounts; determining whether a refresh operation needs to be performed on the first physical erasing unit according to first error bit amounts; in response to no need to perform the refresh operation on the first physical erasing unit, selecting a first word line with the largest first error bit amount in the word lines, and detecting a voltage distribution variation of the first word line; and calculating a new read count threshold of the first physical erasing unit according to the voltage distribution variation.

公开(公告)号：US20240289022A1

公开(公告)日：2024-08-29

申请号：US18190055

申请日：2023-03-24

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Yin Ping Gao ,  Qi-Ao Zhu ,  Kuai Cao ,  Dong Sheng Rao

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0679

Abstract: A data arrangement method based on file system, a memory storage device and a memory control circuit unit are disclosed. The method includes: analyzing a file system stored in a system region to obtain a plurality of first logical units to which a first file belongs and first distribution information of a plurality of first physical units in a storage region, wherein the first physical units are mapped by the first logical units; determining whether to activate a data arrangement operation on the first file according to the first distribution information; after the data arrangement operation on the first file is activated, reading first data belonging to the first file from the first physical units; and writing, sequentially, the read first data to at least one second physical unit in the storage region.

公开(公告)号：US12099753B2

公开(公告)日：2024-09-24

申请号：US18190152

申请日：2023-03-27

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Ya Jie Guo ,  En Yang Wang ,  Kuai Cao ,  Dong Dong Yao ,  Yun Peng Zhang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A mapping table updating method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving, a plurality of operation commands from a host system; performing a first table updating operation according to a first operation command and a third operation command among the operation commands to read and update a first sub-mapping table and a third sub-mapping table from a rewritable non-volatile memory module; and after the first table updating operation is finished, performing a second table updating operation according to a second operation command among the operation commands to read and update a second sub-mapping table from the rewritable non-volatile memory module.

公开(公告)号：US20240289051A1

公开(公告)日：2024-08-29

申请号：US18190152

申请日：2023-03-27

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Ya Jie Guo ,  En Yang Wang ,  Kuai Cao ,  Dong Dong Yao ,  Yun Peng Zhang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A mapping table updating method, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving, a plurality of operation commands from a host system; performing a first table updating operation according to a first operation command and a third operation command among the operation commands to read and update a first sub-mapping table and a third sub-mapping table from a rewritable non-volatile memory module; and after the first table updating operation is finished, performing a second table updating operation according to a second operation command among the operation commands to read and update a second sub-mapping table from the rewritable non-volatile memory module.

公开(公告)号：US20230161489A1

公开(公告)日：2023-05-25

申请号：US17555487

申请日：2021-12-19

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Jing Zhang ,  Kuai Cao ,  Xin Wang

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: A data storing allocation method, a memory storage apparatus, and a memory control circuit unit are provided. The method includes the following. A plurality of data writing speeds of a plurality of memory units are detected. An initial write volume of each memory unit is determined according to a number of dies in each memory unit. At least one compensation data volume is calculated according to the data writing speeds and the initial write volume of each memory unit. A write data corresponding to a write command is written to the memory units according to the initial write volume of each memory unit and the at least one compensation data volume.

公开(公告)号：US20240289017A1

公开(公告)日：2024-08-29

申请号：US18190147

申请日：2023-03-27

Applicant: Hefei Core Storage Electronic Limited

Inventor： Chih-Ling Wang ,  Dong Dong Yao ,  Yun Peng Zhang ,  Kuai Cao ,  En Yang Wang ,  Wen Qing Lv

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0634 ,  G06F3/0679

Abstract: A performance match method of memory, a memory storage device and a memory control circuit unit are disclosed. The method includes: receiving a performance match command from a host system; in response to the performance match command, adjusting an operation setting of a memory storage device to match a performance of the memory storage device with a performance requirement of the host system; and interacting with the host system based on the adjusted operation setting.

公开(公告)号：US20230185329A1

公开(公告)日：2023-06-15

申请号：US17572654

申请日：2022-01-11

Applicant: Hefei Core Storage Electronic Limited

Inventor： Yang Chen ,  Yue Hu ,  Dong Sheng Rao ,  Kuai Cao ,  Qin Qin Tao

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: A timer calibration method and an electronic device are disclosed. The method includes: performing a fitting operation according to a clock frequency of a clock device and an output of a timer to generate a fitting function; obtaining a first value output by the timer; and adjusting the first value to be a second value according to the fitting function to calibrate the timer.

公开(公告)号：US20230127512A1

公开(公告)日：2023-04-27

申请号：US17533020

申请日：2021-11-22

Applicant: Hefei Core Storage Electronic Limited

Inventor： Qi-Ao Zhu ,  Jing Zhang ,  Kuai Cao ,  Xin Wang ,  Xu Hui Cheng ,  Dong Sheng Rao

IPC: G06F3/06 ,  G06F13/16 ,  G06F1/3234 ,  G06F1/3287

Abstract: A memory performance optimization method, a memory control circuit unit, and a memory storage device are provided. The method includes the following. An idle time of the memory storage device is counted in an active mode. The memory storage device is instructed to enter a first low electricity consumption mode from the active mode in response to the idle time being greater than an idle threshold. A first waiting time of the memory storage device is counted in the first low electricity consumption mode. The memory storage device is instructed to enter a second low electricity consumption mode from the first low electricity consumption mode in response to the first waiting time being greater than a first waiting threshold. Electricity consumption of the second low electricity consumption mode is lower than electricity consumption of the first low electricity consumption mode.