AC-COUPLING STRUCTURE IN ELECTRICAL CABLED INTERCONNECT

    公开(公告)号:US20240055157A1

    公开(公告)日:2024-02-15

    申请号:US18491907

    申请日:2023-10-23

    Abstract: A signal cable for an AC-coupled link, may include: a signal conductor; a dielectric surrounding the signal conductor; and a ground sheath having a conductive layer disposed at least partially around the conductor such that the dielectric is positioned between the ground sheath and the signal conductor, wherein the conductive layer comprises a first portion extending in a first direction along the cable and a second portion extending in a second direction, opposite the first direction, along the cable and further wherein the first and second portions of the conductive layer are separated from each other by a gap, the gap being dimensioned to provide a determined amount of capacitance in series in the ground sheath. The gap may form a complete separation between the first and second portions of the conductive layer.

    DOUBLE STUB TRANSMISSION LINE FOR SUPPRESSION OF HARMONICS

    公开(公告)号:US20220418093A1

    公开(公告)日:2022-12-29

    申请号:US17362734

    申请日:2021-06-29

    Abstract: One aspect provides a printed circuit board (PCB). The PCB includes a transmission line to transmit signals of a desired frequency, a first stub coupled to the transmission line at a first location, and a second stub coupled to the transmission line at a second location. The first stub is to filter out signals of a first frequency, the second stub is to filter out signals of a second frequency, and the first and second stubs are positioned such that an insertion loss of the transmitted signals of the desired frequency is substantially minimized.

    Bit error ratio tests
    5.
    发明授权

    公开(公告)号:US09712263B1

    公开(公告)日:2017-07-18

    申请号:US15254098

    申请日:2016-09-01

    CPC classification number: H04B17/336 H04B17/318 H04L1/203 H04L1/242

    Abstract: An example communications device may include a slicer that may generate a digital output signal by thresholding a received signal according to variably set timing and voltage parameters. Testing circuitry may determine expected bit error ratios for multiple time-voltage slices by performing test operations corresponding respectively to the multiple time-voltage slices. Each of the test operations may include setting the timing and voltage parameters of the slicer based on the corresponding time-voltage slice, periodically measuring a bit error ratio based on the digital output signal and determining a confidence level for the measured bit error ratio, and in response to the determined confidence level equaling or exceeding a specified value, designating a current value of the measured bit-error ratio as the expected bit error ratio for the corresponding time-voltage slice and ending the test operation.

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