公开(公告)号：US20160276995A1

公开(公告)日：2016-09-22

申请号：US15073622

申请日：2016-03-17

Applicant: INNOCHIPS TECHNOLOGY CO., LTD.

Inventor： In Kil PARK ,  Tae Hyung NOH ,  Gyeong Tae KIM ,  Myung Ho LEE ,  Tae Geun SEO ,  Min Soo LEE ,  Song Yeon LEE

IPC: H03H1/00 ,  H01F27/28 ,  H01G4/30 ,  H01G4/40 ,  H03H7/01 ,  H01G4/005

CPC classification number: H03H1/00 ,  H01F17/0013 ,  H01F27/2804 ,  H01F2017/002 ,  H01F2017/0026 ,  H01F2027/2809 ,  H01G4/005 ,  H01G4/232 ,  H01G4/30 ,  H01G4/40 ,  H03H7/0115 ,  H03H2001/0085

Abstract: Provided is a laminated chip device including a first laminate in which a plurality of conductor patterns formed on a plurality of sheets are connected to each other through a via formed to penetrate at least a sheet, and a second laminate provided over or below the first laminate and having a plurality of internal electrode patterns formed on a plurality of sheets, and the internal electrode patterns have a non-conductive region in at least a portion of an area corresponding to the via.

Abstract translation: 提供了一种层叠芯片装置，其包括：第一层压体，其中形成在多个片材上的多个导体图案通过形成为穿透至少一个片材的通孔彼此连接;以及第二层压体，其设置在第一层压体上方或下方 并且具有形成在多个片材上的多个内部电极图案，并且内部电极图案在与通孔对应的区域的至少一部分中具有非导电区域。

公开(公告)号：US20150214916A1

公开(公告)日：2015-07-30

申请号：US14608115

申请日：2015-01-28

Applicant: INNOCHIPS TECHNOLOGY CO., LTD.

Inventor： In Kil PARK ,  Tae Hyung NOH ,  Gyeong Tae KIM ,  Tae Geun SEO ,  Myung Ho LEE ,  Min Soo LEE

IPC: H03H7/01 ,  H03H7/06

CPC classification number: H03H7/0115 ,  H03H2001/0085

Abstract: The present disclosure relates to a stacked chip device including a first stack unit comprising a plurality of electrode patterns respectively disposed for a unit device region and common electrode patterns formed to be connected to cross the unit device regions, a second stack unit disposed on a top portion of the first stack unit and comprising a plurality of first conductor patterns, and a third stack unit disposed on a bottom portion of the first stack unit and comprising a plurality of second conductor patterns, wherein the first and second conductor patterns are formed on a plurality of sheets, the first and second conductor patterns formed on one sheet are formed across a plurality of unit device regions, and the first and second conductor patterns are connected vertically through vias formed penetrating through at least some of the sheets.

Abstract translation: 本公开涉及一种堆叠式芯片装置，其包括：第一堆叠单元，包括分别设置用于单位装置区域的多个电极图案和形成为连接以跨过单位装置区域的公共电极图案;第二堆叠单元，设置在顶部 第一堆叠单元的一部分并且包括多个第一导体图案，以及设置在第一堆叠单元的底部上并且包括多个第二导体图案的第三堆叠单元，其中第一和第二导体图案形成在第一堆叠单元 多个片材，形成在一个片材上的第一和第二导体图案跨越多个单元器件区域形成，并且第一和第二导体图案垂直地穿过穿过至少一些片材的通孔。