公开(公告)号：US12288750B2

公开(公告)日：2025-04-29

申请号：US17485208

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Beomseok Choi ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  Adel Elsherbini

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

公开(公告)号：US20240063183A1

公开(公告)日：2024-02-22

申请号：US17820982

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kaladhar Radhakrishnan ,  Anne Augustine ,  Beomseok Choi ,  Kimin Jun ,  Omkar G. Karhade ,  Shawna M. Liff ,  Julien Sebot ,  Johanna M. Swan ,  Krishna Vasanth Valavala

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/48

CPC classification number: H01L25/0655 ,  H01L24/08 ,  H01L24/16 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/80 ,  H01L23/481 ,  H01L2224/16225 ,  H01L2224/08145 ,  H01L2924/3512 ,  H01L2924/3841 ,  H01L2924/37001 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of monolithic wafers and disaggregated integrated circuit (IC) dies, adjacent layers being coupled together by first interconnects having a pitch less than 10 micrometers between adjacent first interconnects, the disaggregated IC dies arranged with portions of the monolithic wafers into modular sub-assemblies; and a package substrate coupled to the modular sub-assemblies by second interconnects having a pitch greater than 10 micrometers between adjacent second interconnects. The disaggregated IC dies are surrounded laterally by a dielectric material, and the disaggregated IC dies are arranged with portions of the monolithic wafers such that a voltage regulator circuit in a first layer of the plurality of layers, a compute circuit in a second layer of the plurality of layers, and a memory circuit in a third layer of the plurality of layers are conductively coupled together in an intra-modular power delivery circuitry.

公开(公告)号：US20210398895A1

公开(公告)日：2021-12-23

申请号：US16907797

申请日：2020-06-22

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Georgios Dogiamis ,  Beomseok Choi ,  Henning Braunisch ,  William Lambert ,  Krishna Bharath ,  Johanna Swan

IPC: H01L23/50 ,  H05K1/18 ,  H01L23/367 ,  H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

公开(公告)号：US20200006292A1

公开(公告)日：2020-01-02

申请号：US16022515

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Beomseok Choi ,  Siddharth Kulasekaran ,  Kaladhar Radhakrishnan

IPC: H01L25/065 ,  H01L25/18 ,  H02M1/08

Abstract: A semiconductor package is provided, which includes a first die and a second die. The first die includes a first section of a power converter, and the second die includes a second section of the power converter. The power converter may include a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches. The PM circuitry may include a first part and a second part. The first section of the power converter in the first die may include the first part of the PM circuitry, and the second section of the power converter in the second die may include the second part of the PM circuitry.

公开(公告)号：US20200006250A1

公开(公告)日：2020-01-02

申请号：US16024007

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Michael J. Hill ,  Mathew Manusharow ,  Beomseok Choi ,  Digvijay Raorane

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/64 ,  H01L25/18 ,  H01F27/28 ,  H01F38/14 ,  G06F1/28

Abstract: An apparatus may include a substrate, one or more integrated circuit dies on the substrate, and a stiffener affixed to one or more sides of the substrate. One or more sections of the stiffener may include a magnetic material. The apparatus may further include an inductive circuit element comprising one or more conductive structures wrapped around the magnetic material.

公开(公告)号：US12266840B2

公开(公告)日：2025-04-01

申请号：US17359138

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Johanna Swan ,  Adel Elsherbini ,  Shawna Liff ,  Beomseok Choi ,  Qiang Yu

IPC: H01P3/16 ,  H01L23/538 ,  H01L23/66 ,  H01L25/065 ,  H01P1/208 ,  H01P5/107

Abstract: Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.

公开(公告)号：US20240114622A1

公开(公告)日：2024-04-04

申请号：US17956338

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Srinivas Venkata Ramanuja Pietambaram ,  Tarek A. Ibrahim ,  Cary Kuliasha ,  Siddharth K. Alur ,  Jung Kyu Han ,  Beomseok Choi ,  Russell K. Mortensen ,  Andrew Collins ,  Haobo Chen ,  Brandon C. Marin

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/538 ,  H01L23/64 ,  H01L25/065 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K1/185 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/645 ,  H01L25/0655 ,  H05K3/0047 ,  H05K3/4644 ,  H05K2201/1003 ,  H05K2201/10674

Abstract: An electronic device includes a substrate including a core layer; a cavity formed in the core layer, wherein the cavity includes sidewalls plated with a conductive material; a prefabricated passive electronic component disposed in the cavity; and a cavity sidewall connection providing electrical continuity from the plated cavity sidewalls to a first surface of the substrate and to a second surface of the substrate.

公开(公告)号：US20230097714A1

公开(公告)日：2023-03-30

申请号：US17485208

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Beomseok Choi ,  Krishna Bharath ,  Kaladhar Radhakrishnan ,  Adel Elsherbini

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00

Abstract: In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.

公开(公告)号：US20230095608A1

公开(公告)日：2023-03-30

申请号：US17485250

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Aleksandar Aleksov ,  Feras Eid ,  Henning Braunisch ,  Thomas L. Sounart ,  Johanna Swan ,  Beomseok Choi ,  Krishna Bharath ,  William J. Lambert ,  Kaladhar Radhakrishnan

IPC: H05K3/14 ,  H05K3/10 ,  H05K3/30 ,  H01L21/768 ,  H01L21/82

Abstract: A embedded passive structure, a microelectronic system, and an integrated circuit device assembly, and a method of forming the embedded passive structure. The embedded passive structure includes a base layer; a passive device attached to the base layer; a first power plane comprising metal and adjacent an upper surface of the base layer, the first power plane having a portion electrically coupled to a terminal of the passive device, wherein an upper surface of a combination of the first power plane and the passive device defines a recess; a second power plane comprising metal, the second power plane at least partially within the recess and having a lower surface that conforms with the upper surface of the combination; and a liner including a dielectric layer between the first power plane and the second power plane.

公开(公告)号：US11211866B2

公开(公告)日：2021-12-28

申请号：US16642268

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： William J. Lambert ,  Kaladhar Radhakrishnan ,  Beomseok Choi ,  Krishna Bharath ,  Michael J. Hill

IPC: H02M3/158 ,  G01R19/165 ,  G05F1/46 ,  H01F21/02 ,  H02M1/00 ,  H02M3/156

Abstract: An adjustable inductance system includes a plurality of inductor modules coupled to a corresponding plurality of loads and a pool of at least one floating inductor module that may be coupled in parallel with any one of the plurality of inductor modules. A control circuit monitors the current drawn through the inductor module by the load. If current draw exceeds a threshold, the control circuit couples a floating inductor module to the load. Using the current drawn by the load, the control circuit determines an appropriate inductance value and determines an appropriate inductor configuration for the inductor module, the floating inductor module, or both the inductor module and the floating inductor module to achieve the determined inductance value. The control circuit causes switching elements to transition to a state or position to achieve the inductor configuration.