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公开(公告)号：US10241794B2
公开(公告)日：2019-03-26
申请号：US15391703
申请日：2016-12-27
Applicant: Intel Corporation
Inventor： Sergey P. Scherbinin , Jayesh Iyer , Alexander Y. Ostanevich , Dmitry Maslennikov , Denis G. Motin , Alexander V. Ermolovich , Andrey Chudnovets , Sergey A. Rozhkov , Boris A. Babayan
Abstract: Embodiments described herein generally relate to the field of multi-strand out-of-order loop processing, and, more specifically, to apparatus and methods to support counted loop exits in a multi-strand loop processor. In one embodiment, a processor includes a loop accelerator comprising a strand documentation buffer and a plurality of strand execution circuits; and a binary translator to receive a plurality of loop instructions, divide the plurality of loop instructions into a plurality of strands, and store a strand documentation for each of the plurality of strands into the strand documentation buffer, each strand documentation indicating at least a number of iterations; wherein the binary translator further causes the loop accelerator to execute the plurality of strands asynchronously and in parallel using the plurality of strand execution circuits, wherein each of the strand execution circuits repeats the strand for the number of iterations indicated in the strand documentation associated with the strand.
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2.发明授权公开(公告)号：US10579378B2
公开(公告)日：2020-03-03
申请号：US14228016
申请日：2014-03-27
Applicant: Intel Corporation
Inventor： Edward T. Grochowski , Victor W. Lee , Sergey A. Rozhkov , Boris A. Babayan
IPC: G06F9/30
Abstract: An apparatus and method are described for executing instructions using a predicate register. For example, one embodiment of a processor comprises: a register set including a predicate register to store a set of predicate condition bits, the predicate condition bits specifying whether results of a particular predicated instruction sequence are to be retained or discarded; and predicate execution logic to execute a first predicate instruction to indicate a start of a new predicated instruction sequence by copying a condition value from a processor control register in the register set to the predicate register. In a further embodiment, the predicate condition bits in the predicate register are to be shifted in response to the first predicate instruction to free space within the predicate register for the new condition value associated with the new predicated instruction sequence.
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3.发明申请INSTRUCTION AND LOGIC FOR IDENTIFYING INSTRUCTIONS FOR RETIREMENT IN A MULTI-STRAND OUT-OF-ORDER PROCESSOR 审中-公开用于识别在多个不合格订单处理程序中退出的说明的指令和逻辑公开(公告)号：US20160314000A1
公开(公告)日：2016-10-27
申请号：US15103765
申请日：2013-12-23
Applicant: Intel Corporation
Inventor： Nikolay Kosarev , Sergey Y. Shishlov , Jayesh Iyer , Alexander V. Butuzov , Boris A. Babayan , Andrey Kluchnikov
CPC classification number: G06F9/3855 , G06F9/3005 , G06F9/30145 , G06F9/384 , G06F9/3851 , G06F9/3857 , G06F9/3869
Abstract: A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.
Abstract translation: 处理器包括执行无序指令流的第一逻辑，划分成多个线的指令流，指令流以及按程序顺序（PO）排序的每个线。 处理器还包括第二逻辑，用于确定指令流中最旧的未分配指令，并将最旧未分配指令的关联PO值存储为执行指令指针。 指令流包括调度和未分配的指令。 处理器还包括第三逻辑，用于确定指令流中最近退休的指令，并将最近退休的指令的相关联的PO值存储为退休指针;第四逻辑，用于选择退休指针和退出指令之间的指令范围; 执行指令指针，以及第五个逻辑，以标识符合退休条件的指令范围。
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公开(公告)号：US10133582B2
公开(公告)日：2018-11-20
申请号：US15103765
申请日：2013-12-23
Applicant: Intel Corporation
Inventor： Nikolay Kosarev , Sergey Y. Shishlov , Jayesh Iyer , Alexander V. Butuzov , Boris A. Babayan , Andrey Kluchnikov
Abstract: A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.
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公开(公告)号：US20180181400A1
公开(公告)日：2018-06-28
申请号：US15391703
申请日：2016-12-27
Applicant: Intel Corporation
Inventor： Sergey P. Scherbinin , Jayesh Iyer , Alexander Y. Ostanevich , Dmitry Maslennikov , Denis G. Motin , Alexander V. Ermolovich , Andrey Chudnovets , Sergey A. Rozhkov , Boris A. Babayan
IPC: G06F9/32
CPC classification number: G06F9/325 , G06F8/443 , G06F8/4452 , G06F8/452 , G06F9/30065 , G06F9/381 , G06F9/3851 , G06F9/45516
Abstract: Embodiments described herein generally relate to the field of multi-strand out-of-order loop processing, and, more specifically, to apparatus and methods to support counted loop exits in a multi-strand loop processor. In one embodiment, a processor includes a loop accelerator comprising a strand documentation buffer and a plurality of strand execution circuits; and a binary translator to receive a plurality of loop instructions, divide the plurality of loop instructions into a plurality of strands, and store a strand documentation for each of the plurality of strands into the strand documentation buffer, each strand documentation indicating at least a number of iterations; wherein the binary translator further causes the loop accelerator to execute the plurality of strands asynchronously and in parallel using the plurality of strand execution circuits, wherein each of the strand execution circuits repeats the strand for the number of iterations indicated in the strand documentation associated with the strand.
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Patent Agency Ranking
公开(公告)号：US20160364239A1
公开(公告)日：2016-12-15
申请号：US15121348
申请日：2014-03-27
Applicant: INTEL CORPORATION
Inventor： Anton Lechenko , Andrey Efimov , Sergey Y. Shishlov , Andrey Kluchnikov , Kamil Garifullin , Igor Burovenko , Boris A. Babayan
CPC classification number: G06F9/3855 , G06F9/30043 , G06F9/30145 , G06F9/3824 , G06F9/3851 , G06F9/3857
Abstract: A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.
Abstract translation: 处理器包括执行无序指令流的逻辑。 指令流被分成多个线，并且其指令和流内的指令按程序顺序（PO）排序。 处理器还包括用于识别指令流中最旧的未分配指令并将其相关联的PO记录为执行的指令指针的逻辑，识别指令流中最近提交的存储指令并将其相关联的PO记录为存储承诺指针，搜索 具有PO的指针小于执行指令指针，在具有PO小于搜索指针的PO的存储缓冲器中识别第一组存储指令，并且有资格进行承诺，评估第一组存储指令是否大于多个读取端口 存储缓冲区，并调整搜索指针。
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公开(公告)号：US10241801B2
公开(公告)日：2019-03-26
申请号：US15390194
申请日：2016-12-23
Applicant: Intel Corporation
Inventor： Jayesh Iyer , Sergey P. Scherbinin , Alexander Y. Ostanevich , Dmitry M. Maslennikov , Denis G. Motin , Alexander V. Ermolovich , Andrey Chudnovets , Sergey A. Rozhkov , Boris A. Babayan
Abstract: An apparatus includes a register file and a binary translator to create a plurality of strands and a plurality of iteration windows, where each iteration window of the plurality of iteration windows is allocated a set of continuous registers of the register file. The apparatus further includes a buffer to store strand documentation for a strand from the plurality of strands, where the strand documentation for the strand is to include an indication of a current register base for the strand. The apparatus further includes an execution circuit to execute an instruction to update the current register base for the strand in the strand documentation for the strand based on a fixed step value and an iteration window size.
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8.发明申请公开(公告)号：US20170235578A1
公开(公告)日：2017-08-17
申请号：US15391709
申请日：2016-12-27
Applicant: Intel Corporation
Inventor： Boris A. Babayan , Vladimir M. Pentkovski , Alexander V. Butuzov , Sergey Y. Shishlov , Alexey Y. Sivtsov , Nikolay Kosarev
CPC classification number: G06F9/3855 , G06F9/30087 , G06F9/3016 , G06F9/3017 , G06F9/34 , G06F9/3802 , G06F9/3824 , G06F9/3838 , G06F9/3851 , G06F9/3891
Abstract: In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for scheduling instructions in a multi-strand out-of-order processor. For example, an apparatus for scheduling instructions in a multi-strand out-of-order processor includes an out-of-order instruction fetch unit to retrieve a plurality of interdependent instructions for execution from a multi-strand representation of a sequential program listing; an instruction scheduling unit to schedule the execution of the plurality of interdependent instructions based at least in part on operand synchronization bits encoded within each of the plurality of interdependent instructions; and a plurality of execution units to execute at least a subset of the plurality of interdependent instructions in parallel.
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9.发明授权Hardware apparatuses and methods to control access to a multiple bank data cache 有权用于控制对多组数据高速缓存的访问的硬件设备和方法公开(公告)号：US09471501B2
公开(公告)日：2016-10-18
申请号：US14498902
申请日：2014-09-26
Applicant: INTEL CORPORATION
Inventor： Andrey Kluchnikov , Jayesh Iyer , Sergey Y. Shishlov , Boris A. Babayan
CPC classification number: G06F12/0844 , G06F3/0613 , G06F3/0637 , G06F3/0659 , G06F3/0673 , G06F9/52 , G06F12/0811 , G06F12/084 , G06F12/0842 , G06F12/0875 , G06F13/18 , G06F2212/1008 , G06F2212/1016 , G06F2212/251 , G06F2212/452
Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.
Abstract translation: 描述了控制对多存储体数据缓存的访问的方法和装置。 在一个实施例中，处理器包括冲突解决逻辑，以检测被调度以在相同时钟周期内访问多存储体数据高速缓存的相同存储体的多个指令，并且为预定访问最高总数的多个指令的指令授予访问优先级 银行多银行数据缓存。 在另一个实施例中，一种方法包括检测被调度以在相同时钟周期内访问多存储体数据高速缓存的同一个存储体的多个指令，以及授予被调度以访问该多个存储体中多个存储体的最高总数组的多个指令的指令的访问优先级 银行数据缓存。
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公开(公告)号：US10514927B2
公开(公告)日：2019-12-24
申请号：US15121348
申请日：2014-03-27
Applicant: Intel Corporation
Inventor： Anton Lechanka , Andrey Efimov , Sergey Y. Shishlov , Andrey Kluchnikov , Kamil Garifullin , Igor Burovenko , Boris A. Babayan
Abstract: A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.
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