公开(公告)号：US20160314000A1

公开(公告)日：2016-10-27

申请号：US15103765

申请日：2013-12-23

Applicant: Intel Corporation

Inventor： Nikolay Kosarev ,  Sergey Y. Shishlov ,  Jayesh Iyer ,  Alexander V. Butuzov ,  Boris A. Babayan ,  Andrey Kluchnikov

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3855 ,  G06F9/3005 ,  G06F9/30145 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3869

Abstract: A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.

Abstract translation: 处理器包括执行无序指令流的第一逻辑，划分成多个线的指令流，指令流以及按程序顺序（PO）排序的每个线。 处理器还包括第二逻辑，用于确定指令流中最旧的未分配指令，并将最旧未分配指令的关联PO值存储为执行指令指针。 指令流包括调度和未分配的指令。 处理器还包括第三逻辑，用于确定指令流中最近退休的指令，并将最近退休的指令的相关联的PO值存储为退休指针;第四逻辑，用于选择退休指针和退出指令之间的指令范围; 执行指令指针，以及第五个逻辑，以标识符合退休条件的指令范围。

公开(公告)号：US10095522B2

公开(公告)日：2018-10-09

申请号：US14581268

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Kamil Garifullin ,  Stanislav Shwartsman ,  Lihu Rappoport ,  Zeev Sperber ,  Pavel I. Kryukov ,  Andrey Kluchnikov ,  Igor Yanover ,  George Leifman ,  Alex Gerber ,  Jared W. Stark

IPC: G06F9/312 ,  G06F9/38 ,  G06F9/30

Abstract: A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.

公开(公告)号：US10133582B2

公开(公告)日：2018-11-20

申请号：US15103765

申请日：2013-12-23

Applicant: Intel Corporation

Inventor： Nikolay Kosarev ,  Sergey Y. Shishlov ,  Jayesh Iyer ,  Alexander V. Butuzov ,  Boris A. Babayan ,  Andrey Kluchnikov

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor includes a first logic to execute an instruction stream out-of-order, the instruction stream divided into a plurality of strands, the instruction stream and each strand ordered by program order (PO). The processor also includes a second logic to determine an oldest undispatched instruction in the instruction stream and store an associated PO value of the oldest undispatched instruction as an executed instruction pointer. The instruction stream includes dispatched and undispatched instructions. The processor also includes a third logic to determine a most recently retired instruction in the instruction stream and store an associated PO value of the most recently retired instruction as a retirement pointer, a fourth logic to select a range of instructions between the retirement pointer and the executed instruction pointer, and a fifth logic to identify the range of instructions as eligible for retirement.

公开(公告)号：US20160364239A1

公开(公告)日：2016-12-15

申请号：US15121348

申请日：2014-03-27

Applicant: INTEL CORPORATION

Inventor： Anton Lechenko ,  Andrey Efimov ,  Sergey Y. Shishlov ,  Andrey Kluchnikov ,  Kamil Garifullin ,  Igor Burovenko ,  Boris A. Babayan

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3855 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3857

Abstract: A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.

Abstract translation: 处理器包括执行无序指令流的逻辑。 指令流被分成多个线，并且其指令和流内的指令按程序顺序（PO）排序。 处理器还包括用于识别指令流中最旧的未分配指令并将其相关联的PO记录为执行的指令指针的逻辑，识别指令流中最近提交的存储指令并将其相关联的PO记录为存储承诺指针，搜索 具有PO的指针小于执行指令指针，在具有PO小于搜索指针的PO的存储缓冲器中识别第一组存储指令，并且有资格进行承诺，评估第一组存储指令是否大于多个读取端口 存储缓冲区，并调整搜索指针。

公开(公告)号：US09471501B2

公开(公告)日：2016-10-18

申请号：US14498902

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Andrey Kluchnikov ,  Jayesh Iyer ,  Sergey Y. Shishlov ,  Boris A. Babayan

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/18

CPC classification number: G06F12/0844 ,  G06F3/0613 ,  G06F3/0637 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F13/18 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/251 ,  G06F2212/452

Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.

Abstract translation: 描述了控制对多存储体数据缓存的访问的方法和装置。 在一个实施例中，处理器包括冲突解决逻辑，以检测被调度以在相同时钟周期内访问多存储体数据高速缓存的相同存储体的多个指令，并且为预定访问最高总数的多个指令的指令授予访问优先级 银行多银行数据缓存。 在另一个实施例中，一种方法包括检测被调度以在相同时钟周期内访问多存储体数据高速缓存的同一个存储体的多个指令，以及授予被调度以访问该多个存储体中多个存储体的最高总数组的多个指令的指令的访问优先级 银行数据缓存。

公开(公告)号：US10514927B2

公开(公告)日：2019-12-24

申请号：US15121348

申请日：2014-03-27

Applicant: Intel Corporation

Inventor： Anton Lechanka ,  Andrey Efimov ,  Sergey Y. Shishlov ,  Andrey Kluchnikov ,  Kamil Garifullin ,  Igor Burovenko ,  Boris A. Babayan

IPC: G06F9/30 ,  G06F9/38

Abstract: A processor includes logic to execute an instruction stream out-of-order. The instruction stream is divided into a plurality of strands and its instructions and those within the streams are ordered by program order (PO). The processor further includes logic to identify an oldest undispatched instruction in the instruction stream and record its associated PO as an executed instruction pointer, identify a most recently committed store instruction in the instruction stream and record its associated PO as a store commitment pointer, a search pointer with PO less than the execution instruction pointer, identify a first set of store instructions in a store buffer with PO less than the search pointer and eligible for commitment, evaluate whether the first set of store instructions is larger than a number of read ports of the store buffer, and adjust the search pointer.

公开(公告)号：US10095623B2

公开(公告)日：2018-10-09

申请号：US15297084

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Andrey Kluchnikov ,  Jayesh Iyer ,  Sergey Y. Shishlov ,  Boris A. Babayan

IPC: G06F12/00 ,  G06F12/0844 ,  G06F12/0875 ,  G06F3/06 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F13/18 ,  G06F9/52

Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.

公开(公告)号：US20160092367A1

公开(公告)日：2016-03-31

申请号：US14498902

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Andrey Kluchnikov ,  Jayesh Iyer ,  Sergey Y. Shishlov ,  Boris A. Babayan

IPC: G06F12/08

CPC classification number: G06F12/0844 ,  G06F3/0613 ,  G06F3/0637 ,  G06F3/0659 ,  G06F3/0673 ,  G06F9/52 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0875 ,  G06F13/18 ,  G06F2212/1008 ,  G06F2212/1016 ,  G06F2212/251 ,  G06F2212/452

Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.

Abstract translation: 描述了控制对多存储体数据缓存的访问的方法和装置。 在一个实施例中，处理器包括冲突解决逻辑，以检测被调度以在相同时钟周期内访问多存储体数据高速缓存的相同存储体的多个指令，并且为预定访问最高总数的多个指令的指令授予访问优先级 银行多银行数据缓存。 在另一个实施例中，一种方法包括检测被调度以在相同时钟周期内访问多存储体数据高速缓存的同一个存储体的多个指令，以及授予被调度以访问该多个存储体中多个存储体的最高总数组的多个指令的指令的访问优先级 银行数据缓存。