公开(公告)号：US09354694B2

公开(公告)日：2016-05-31

申请号：US13827738

申请日：2013-03-14

Applicant: Intel Corporation

Inventor： David Pardo Keppel ,  Jawad Nasrullah

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括使得至少一个核心根据ON-OFF密钥协议的功率控制周期进行操作的逻辑，所述功率控制周期包括多个接通时间和多个关闭时间，其中关闭时间各自对应于 包括处理器的平台的最大关闭时间。 描述和要求保护其他实施例。

公开(公告)号：US10168765B2

公开(公告)日：2019-01-01

申请号：US15144922

申请日：2016-05-03

Applicant: Intel Corporation

Inventor： David Pardo Keppel ,  Jawad Nasrullah

IPC: G06F1/32

Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.

公开(公告)号：US10061587B2

公开(公告)日：2018-08-28

申请号：US14496113

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： David Pardo Keppel ,  Denis M. Khartikov ,  Fernando LaTorre ,  Marc Lupon ,  Grigorios Magklis ,  Naveen Neelakantam ,  Georgios Tournavitis ,  Polychronis Xekalakis

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30185 ,  G06F9/384 ,  G06F9/3857

Abstract: A processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register.

公开(公告)号：US20220206955A1

公开(公告)日：2022-06-30

申请号：US17134392

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： David Pardo Keppel

IPC: G06F12/1036 ,  G06F12/1045

Abstract: A translation lookaside buffer (TLB) having a fixed sub-TLB and a configurable sub-TLB and methods of using the TLB are provided. The TLB includes a fixed sub-TLB and a configurable sub-TLB. The fixed sub-TLB, during runtime, may store a first plurality of TLB entries corresponding to a first page size set. The configurable sub-TLB, during runtime, is configurable to store a second plurality of TLB entries of a second page size set. The second page size set includes at least a first page size of the first page size set and includes at least a second page size not of the first page size set.

公开(公告)号：US11055232B2

公开(公告)日：2021-07-06

申请号：US16370848

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： David Pardo Keppel ,  Binh Pham

IPC: G06F12/1036 ,  G06F12/1045 ,  G06F12/1009

Abstract: A processor includes a translation lookaside buffer (TLB) to store a TLB entry, wherein the TLB entry comprises a first set of valid bits to identify if the first TLB entry corresponds to a virtual address from a memory access request, wherein the valid bits are set based on a first page size associated with the TLB entry from a first set of different page sizes assigned to a first probe group; and a control circuit to probe the TLB for each page size of the first set of different page sizes assigned to the first probe group in a single probe cycle to determine if the TLB entry corresponds to the virtual address from the memory access request.

公开(公告)号：US09342403B2

公开(公告)日：2016-05-17

申请号：US14228555

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： David Pardo Keppel ,  Helia Naeimi ,  Jawad Nasrullah

IPC: G06F11/10

CPC classification number: G06F11/106 ,  G06F11/1016 ,  G06F2212/68

Abstract: An apparatus and method for scrubbing spin transfer torque (STT) memory. For example, one embodiment of a apparatus comprises: a memory subsystem including at least one spin transfer torque (STT) memory, the STT memory arranged into one or more entries; and a scrub engine to ensure that the entries of the STT contain valid data, the scrub engine including analysis and processing logic to determine, for each entry, whether a specified scrubbing interval has expired and, if so, then to invalidate the entry or re-fetch data for the entry from a source and, if the scrubbing interval has not expired, then to perform error detection and/or correction on the entry.

Abstract translation: 一种用于清洗自旋转移转矩（STT）存储器的装置和方法。 例如，设备的一个实施例包括：存储器子系统，其包括至少一个自旋转移转矩（STT）存储器，STT存储器被布置成一个或多个条目; 以及擦除引擎，以确保STT的条目包含有效数据，擦洗引擎包括分析和处理逻辑，以确定每个条目是否指定的擦除间隔已过期，如果是，则使该条目或重新生效 - 从源中获取条目的数据，如果擦除间隔尚未过期，则对条目执行错误检测和/或更正。

公开(公告)号：US20160092222A1

公开(公告)日：2016-03-31

申请号：US14496113

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： David Pardo Keppel ,  Denis M. Khartikov ,  Fernando LaTorre ,  Marc Lupon ,  Grigorios Magklis ,  Naveen Neelakantam ,  Georgios Tournavitis ,  Polychronis Xekalakis

IPC: G06F9/30

CPC classification number: G06F9/30185 ,  G06F9/384 ,  G06F9/3857

Abstract: A processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register.

Abstract translation: 处理器包括前端，解码器，分配器和退休单元。 解码器包括用于识别终点范围（EOLR）指示符的逻辑。 EOLR指示符指定体系结构寄存器和不使用体系结构寄存器的代码中的位置。 分配器包括基于EOLR指示器扫描架构寄存器到物理寄存器的映射的逻辑。 分配器还包括生成用于将体系结构寄存器与物理寄存器取消关联的请求的逻辑。 退休单位包括将架构寄存器与物理寄存器取消关联的逻辑。

公开(公告)号：US20160320832A1

公开(公告)日：2016-11-03

申请号：US15144922

申请日：2016-05-03

Applicant: Intel Corporation

Inventor： David Pardo Keppel ,  Jawad Nasrullah

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/324 ,  G06F1/3246 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括使得至少一个核心根据ON-OFF密钥协议的功率控制周期进行操作的逻辑，所述功率控制周期包括多个接通时间和多个关闭时间，其中关闭时间各自对应于 包括处理器的平台的最大关闭时间。 描述和要求保护其他实施例。

公开(公告)号：US09477628B2

公开(公告)日：2016-10-25

申请号：US14040676

申请日：2013-09-28

Applicant: INTEL CORPORATION

Inventor： Allan D. Knies ,  David Pardo Keppel ,  Dong Hyuk Woo ,  Joshua B. Fryman

IPC: G06F15/00 ,  G06F13/40 ,  G06F15/173 ,  G06F9/52 ,  G06F13/14

CPC classification number: G06F13/4068 ,  G06F9/52 ,  G06F15/17318 ,  G06F15/17325

Abstract: A collective communication apparatus and method for parallel computing systems. For example, one embodiment of an apparatus comprises a plurality of processor elements (PEs); collective interconnect logic to dynamically form a virtual collective interconnect (VCI) between the PEs at runtime without global communication among all of the PEs, the VCI defining a logical topology between the PEs in which each PE is directly communicatively coupled to a only a subset of the remaining PEs; and execution logic to execute collective operations across the PEs, wherein one or more of the PEs receive first results from a first portion of the subset of the remaining PEs, perform a portion of the collective operations, and provide second results to a second portion of the subset of the remaining PEs.

Abstract translation: 一种用于并行计算系统的集体通信装置和方法。 例如，设备的一个实施例包括多个处理器元件（PE）; 集体互连逻辑以在运行时动态地在PE之间形成虚拟集体互连（VCI），而不在所有PE之间进行全局通信，VCI在PE之间定义逻辑拓扑，其中每个PE直接通信地耦合到仅一个子集 余下的PE; 以及用于在所述PE之间执行集合操作的执行逻辑，其中所述PE中的一个或多个从所述剩余PE的子集的第一部分接收到第一结果，执行所述集体操作的一部分，并且将第二结果提供给 其余PE的子集。

公开(公告)号：US09329658B2

公开(公告)日：2016-05-03

申请号：US13729376

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： David Pardo Keppel ,  Jawad Nasrullah

IPC: G06F1/32

CPC classification number: G06F1/3206

Abstract: In one embodiment, a processor includes at least one sleep block and a central sleep controller. The at least one sleep block may include at least one execution unit, at least one processor component, and sleep logic. The central sleep controller may be to program the sleep logic to perform at least one sleep transition for the at least one sleep block, and to operate in a first sleep mode. The sleep logic may be to perform the at least one sleep transition for the at least one sleep block without waking the central sleep controller from the first sleep mode. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括至少一个睡眠块和中央睡眠控制器。 至少一个睡眠块可以包括至少一个执行单元，至少一个处理器组件和睡眠逻辑。 中央睡眠控制器可以编程休眠逻辑以对至少一个睡眠块执行至少一个睡眠转换，并且以第一睡眠模式操作。 休眠逻辑可以是对于至少一个睡眠块执行至少一个睡眠转换，而不会使中央睡眠控制器从第一睡眠模式唤醒。 描述和要求保护其他实施例。