公开(公告)号：US09477628B2

公开(公告)日：2016-10-25

申请号：US14040676

申请日：2013-09-28

Applicant: INTEL CORPORATION

Inventor： Allan D. Knies ,  David Pardo Keppel ,  Dong Hyuk Woo ,  Joshua B. Fryman

IPC: G06F15/00 ,  G06F13/40 ,  G06F15/173 ,  G06F9/52 ,  G06F13/14

CPC classification number: G06F13/4068 ,  G06F9/52 ,  G06F15/17318 ,  G06F15/17325

Abstract: A collective communication apparatus and method for parallel computing systems. For example, one embodiment of an apparatus comprises a plurality of processor elements (PEs); collective interconnect logic to dynamically form a virtual collective interconnect (VCI) between the PEs at runtime without global communication among all of the PEs, the VCI defining a logical topology between the PEs in which each PE is directly communicatively coupled to a only a subset of the remaining PEs; and execution logic to execute collective operations across the PEs, wherein one or more of the PEs receive first results from a first portion of the subset of the remaining PEs, perform a portion of the collective operations, and provide second results to a second portion of the subset of the remaining PEs.

Abstract translation: 一种用于并行计算系统的集体通信装置和方法。 例如，设备的一个实施例包括多个处理器元件（PE）; 集体互连逻辑以在运行时动态地在PE之间形成虚拟集体互连（VCI），而不在所有PE之间进行全局通信，VCI在PE之间定义逻辑拓扑，其中每个PE直接通信地耦合到仅一个子集 余下的PE; 以及用于在所述PE之间执行集合操作的执行逻辑，其中所述PE中的一个或多个从所述剩余PE的子集的第一部分接收到第一结果，执行所述集体操作的一部分，并且将第二结果提供给 其余PE的子集。

公开(公告)号：US10409763B2

公开(公告)日：2019-09-10

申请号：US14319265

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： Patrick P. Lai ,  Ethan Schuchman ,  David Keppel ,  Denis M. Khartikov ,  Polychronis Xekalakis ,  Joshua B. Fryman ,  Allan D. Knies ,  Naveen Neelakantam ,  Gregor Stellpflug ,  John H. Kelm ,  Mirem Hyuseinova Seidahmedova ,  Demos Pavlou ,  Jaroslaw Topp

IPC: G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/455

Abstract: Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary translation system; (2) data cache way prediction guided by binary translation code morphing software; (3) fast interpreter hardware support on the data-side; (4) out-of-order retirement; (5) decoupled load retirement in an atomic OOO processor; (6) handling transactional and atomic memory in an out-of-order binary translation based processor; and (7) speculative memory management in a binary translation based out of order processor.

公开(公告)号：US09195465B2

公开(公告)日：2015-11-24

申请号：US13729629

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Varun K. Mohandru ,  Fernando Latorre ,  Li-Gao Zei ,  Allan D. Knies ,  Rami May ,  Lutz Naethke

IPC: G06F9/38 ,  G06F12/08

CPC classification number: G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3863 ,  G06F12/0815 ,  G06F2212/507

Abstract: Responsive to execution of a computer instruction in a current translation window, state indicators associated with a cache line accessed for the execution may be modified. The state indicators may include: a first indicator to indicate whether the computer instruction is a load instruction moved from a subsequent translation window into the current translation window, a second indicator to indicate whether the cache line is modified in a cache responsive to the execution of the computer instruction, a third indicator to indicate whether the cache line is speculatively modified in the cache responsive to the execution of the computer instruction, a fourth indicator to indicate whether the cache line is speculatively loaded by the computer instruction, a fifth indicator to indicate whether a core executing the computer instruction exclusively owns the cache line, and a sixth indicator to indicate whether the cache line is invalid.

Abstract translation: 响应于在当前翻译窗口中执行计算机指令，可以修改与为执行访问的高速缓存行相关联的状态指示符。 状态指示符可以包括：第一指示符，用于指示计算机指令是否是从后续转换窗口移动到当前转换窗口的加载指令;第二指示符，用于指示高速缓存行是否在缓存中被修改，响应于执行 计算机指令，第三指示符，用于指示高速缓存行是否响应于计算机指令的执行在高速缓存中被推测地修改;第四指示符，用于指示高速缓存行是否被计算机指令推测性加载;第五指示符，用于指示 执行计算机指令的核心是否独占拥有高速缓存行，以及指示高速缓存行是否无效的第六指示符。

公开(公告)号：US09459871B2

公开(公告)日：2016-10-04

申请号：US13731377

申请日：2012-12-31

Applicant: INTEL CORPORATION

Inventor： Masha Lipshits ,  Lihu Rappaport ,  Shantanu Gupta ,  Franck Sala ,  Naveen Kumar ,  Allan D. Knies

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32

CPC classification number: G06F9/30065 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3844

Abstract: A method, system, and computer program product for identifying loop information corresponding to a plurality of loop instructions. The loop instructions are stored into a queue. The loop instructions are replayed from the queue for execution. Loop iteration is counted based on the identified loop information. A determination is made of whether the last iteration of the loop is done. If the last iteration is not done, then embodiments continue replaying the loop instructions, until the last iteration is done.

Abstract translation: 一种用于识别对应于多个循环指令的循环信息的方法，系统和计算机程序产品。 循环指令存储到队列中。 循环指令从队列中重播以供执行。 循环迭代根据识别的循环信息进行计数。 确定循环的最后一次迭代是否完成。 如果最后一次迭代未完成，则实施例继续重播循环指令，直到完成最后一次迭代。