公开(公告)号：US09323525B2

公开(公告)日：2016-04-26

申请号：US14190404

申请日：2014-02-26

Applicant: Intel Corporation

Inventor： Daehyun Kim ,  Jong Soo Park ,  Dong Hyuk Woo ,  Richard M. Yoo ,  Christopher J. Hughes

IPC: G06F9/30 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F9/30036 ,  G06F9/30189 ,  G06F9/3887 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/81 ,  G06F2201/88 ,  Y02D10/34

Abstract: In an embodiment, a processor includes a vector execution unit having a plurality of lanes to execute operations on vector operands, a performance monitor coupled to the vector execution unit to maintain information regarding an activity level of the lanes, and a control logic coupled to the performance monitor to control power consumption of the vector execution unit based at least in part on the activity level of at least some of the lanes. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括具有多个通道以执行向量操作数的操作的向量执行单元，耦合到向量执行单元的性能监视器，以维护关于通道的活动级别的信息，以及耦合到该通道的控制逻辑 性能监视器，用于至少部分地基于至少一些通道的活动水平来控制向量执行单元的功率消耗。 描述和要求保护其他实施例。

公开(公告)号：US09606797B2

公开(公告)日：2017-03-28

申请号：US13724633

申请日：2012-12-21

Applicant: Intel Corporation

Inventor： Aniruddha S. Vaidya ,  Anahita Shayesteh ,  Dong Hyuk Woo ,  Saikat Saharoy ,  Mani Azimi

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30181 ,  G06F9/3887

Abstract: In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector instruction is of a first width and the vector execution unit is of a smaller width. The processor further includes a control logic coupled to the vector execution unit to compress a number of execution cycles consumed in execution of the vector instruction when at least some of the individual data elements are not to be operated on by the vector instruction. Other embodiments are described and claimed.

公开(公告)号：US09477628B2

公开(公告)日：2016-10-25

申请号：US14040676

申请日：2013-09-28

Applicant: INTEL CORPORATION

Inventor： Allan D. Knies ,  David Pardo Keppel ,  Dong Hyuk Woo ,  Joshua B. Fryman

IPC: G06F15/00 ,  G06F13/40 ,  G06F15/173 ,  G06F9/52 ,  G06F13/14

CPC classification number: G06F13/4068 ,  G06F9/52 ,  G06F15/17318 ,  G06F15/17325

Abstract: A collective communication apparatus and method for parallel computing systems. For example, one embodiment of an apparatus comprises a plurality of processor elements (PEs); collective interconnect logic to dynamically form a virtual collective interconnect (VCI) between the PEs at runtime without global communication among all of the PEs, the VCI defining a logical topology between the PEs in which each PE is directly communicatively coupled to a only a subset of the remaining PEs; and execution logic to execute collective operations across the PEs, wherein one or more of the PEs receive first results from a first portion of the subset of the remaining PEs, perform a portion of the collective operations, and provide second results to a second portion of the subset of the remaining PEs.

Abstract translation: 一种用于并行计算系统的集体通信装置和方法。 例如，设备的一个实施例包括多个处理器元件（PE）; 集体互连逻辑以在运行时动态地在PE之间形成虚拟集体互连（VCI），而不在所有PE之间进行全局通信，VCI在PE之间定义逻辑拓扑，其中每个PE直接通信地耦合到仅一个子集 余下的PE; 以及用于在所述PE之间执行集合操作的执行逻辑，其中所述PE中的一个或多个从所述剩余PE的子集的第一部分接收到第一结果，执行所述集体操作的一部分，并且将第二结果提供给 其余PE的子集。