公开(公告)号：US09601916B2

公开(公告)日：2017-03-21

申请号：US14483649

申请日：2014-09-11

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Karthik Ns ,  Raghavendra Devappa Sharma ,  Dharmaray Nedalgi ,  Prasad Bhilawadi

IPC: G06K19/00 ,  H02H3/18

CPC classification number: H02H3/18 ,  G06F1/26 ,  G06F1/3212 ,  H04B1/38 ,  H04L25/0272

Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.

公开(公告)号：US20240088887A1

公开(公告)日：2024-03-14

申请号：US17993412

申请日：2022-11-23

Applicant: Intel Corporation

Inventor： Dharmaray Nedalgi ,  Lavanya Manohar Nirikhi

IPC: H03K17/082

CPC classification number: H03K17/0822 ,  H03K2217/0081

Abstract: An apparatus comprises a first supply node to provide a first voltage and a second supply node to provide a second voltage lower than the first voltage. First and second transistors, of a first conductivity type, are coupled in series at a first common node, wherein the first transistor is coupled to the first supply node, and the second transistor is coupled to an output node. Third and fourth transistors, of a second conductivity type, coupled in series at a second common node, wherein the fourth transistor is coupled to a third node that is to provide a third voltage, and the third transistor is coupled to the output node. First impedance circuitry is coupled to a gate terminal of the second transistor, the second supply node, and to a gate terminal of the first transistor.

公开(公告)号：US10938200B2

公开(公告)日：2021-03-02

申请号：US15443161

申请日：2017-02-27

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava ,  Karthik Ns ,  Raghavendra Devappa Sharma ,  Dharmaray Nedalgi ,  Prasad Bhilawadi

IPC: G06K19/00 ,  H02H3/18 ,  G06F1/26 ,  G06F1/3212 ,  H04B1/38 ,  H04L25/02

Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.

公开(公告)号：US10128248B1

公开(公告)日：2018-11-13

申请号：US15650271

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Karthik Ns ,  Dharmaray Nedalgi ,  Vani Deshpande ,  Leonhard Heiss ,  Amit Kumar Srivastava

IPC: H01L29/76 ,  H01L27/105 ,  H01L23/58 ,  H01L23/00

Abstract: An apparatus is provided which comprises: a stack of transistors of a same conductivity type, the stack including a first transistor and a second transistor coupled in series and having a common node; and a feedback transistor of the same conductivity type coupled to the common node and a gate terminal of the first transistor of the stack.