公开(公告)号：US20160164515A1

公开(公告)日：2016-06-09

申请号：US14561477

申请日：2014-12-05

Applicant: Intel Corporation

Inventor： Mayank Goel ,  Prasad Bhilawadi ,  Karthik Ns

IPC: H03K17/687

CPC classification number: H03K17/687 ,  H03K17/165 ,  H03K2217/0027

Abstract: Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.

Abstract translation: 一些实施例包括具有接收电源电压的第一节点，接收第一偏置电压的第二节点，接收地电位的第三节点，耦合在第一节点和第二节点之间的第一电路支路的装置和方法，以及第二电路 分支耦合在第一和第三节点之间。 第一偏置电压被提供给串联耦合的多个晶体管中的第一晶体管的栅极。 第一和第二电路分支被布置成向多个晶体管中的第二晶体管的栅极提供第二偏置电压。 第二偏置电压的值基于第一偏置电压的值。

公开(公告)号：US09774324B2

公开(公告)日：2017-09-26

申请号：US14561477

申请日：2014-12-05

Applicant: Intel Corporation

Inventor： Mayank Goel ,  Prasad Bhilawadi ,  Karthik Ns

IPC: H03K17/687 ,  H03K17/16

CPC classification number: H03K17/687 ,  H03K17/165 ,  H03K2217/0027

Abstract: Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.

公开(公告)号：US09601916B2

公开(公告)日：2017-03-21

申请号：US14483649

申请日：2014-09-11

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Karthik Ns ,  Raghavendra Devappa Sharma ,  Dharmaray Nedalgi ,  Prasad Bhilawadi

IPC: G06K19/00 ,  H02H3/18

CPC classification number: H02H3/18 ,  G06F1/26 ,  G06F1/3212 ,  H04B1/38 ,  H04L25/0272

Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.

公开(公告)号：US10938200B2

公开(公告)日：2021-03-02

申请号：US15443161

申请日：2017-02-27

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava ,  Karthik Ns ,  Raghavendra Devappa Sharma ,  Dharmaray Nedalgi ,  Prasad Bhilawadi

IPC: G06K19/00 ,  H02H3/18 ,  G06F1/26 ,  G06F1/3212 ,  H04B1/38 ,  H04L25/02

Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.

公开(公告)号：US10193548B2

公开(公告)日：2019-01-29

申请号：US15714672

申请日：2017-09-25

Applicant: Intel Corporation

Inventor： Mayank Goel ,  Prasad Bhilawadi ,  Karthik Ns

IPC: H03K17/687 ,  H03K17/16

Abstract: Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.

公开(公告)号：US10128248B1

公开(公告)日：2018-11-13

申请号：US15650271

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Karthik Ns ,  Dharmaray Nedalgi ,  Vani Deshpande ,  Leonhard Heiss ,  Amit Kumar Srivastava

IPC: H01L29/76 ,  H01L27/105 ,  H01L23/58 ,  H01L23/00

Abstract: An apparatus is provided which comprises: a stack of transistors of a same conductivity type, the stack including a first transistor and a second transistor coupled in series and having a common node; and a feedback transistor of the same conductivity type coupled to the common node and a gate terminal of the first transistor of the stack.

公开(公告)号：US20180026631A1

公开(公告)日：2018-01-25

申请号：US15714672

申请日：2017-09-25

Applicant: Intel Corporation

Inventor： Mayank Goel ,  Prasad Bhilawadi ,  Karthik Ns

IPC: H03K17/687 ,  H03K17/16

CPC classification number: H03K17/687 ,  H03K17/165 ,  H03K2217/0027

Abstract: Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to receive ground potential, a first circuit branch coupled between the first and second nodes, and a second circuit branch coupled between the first and third nodes. The first bias voltage is provided to a gate of a first transistor among a plurality of transistors coupled in series. The first and second circuit branches are arranged to provide a second bias voltage to gate of a second transistor among the plurality of transistors. The value of the second bias voltage is based on a value of the first bias voltage.