公开(公告)号：US09601916B2

公开(公告)日：2017-03-21

申请号：US14483649

申请日：2014-09-11

Applicant: Intel Corporation

Inventor： Amit Kumar Srivastava ,  Karthik Ns ,  Raghavendra Devappa Sharma ,  Dharmaray Nedalgi ,  Prasad Bhilawadi

IPC: G06K19/00 ,  H02H3/18

CPC classification number: H02H3/18 ,  G06F1/26 ,  G06F1/3212 ,  H04B1/38 ,  H04L25/0272

Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.

公开(公告)号：US10938200B2

公开(公告)日：2021-03-02

申请号：US15443161

申请日：2017-02-27

Applicant: INTEL CORPORATION

Inventor： Amit Kumar Srivastava ,  Karthik Ns ,  Raghavendra Devappa Sharma ,  Dharmaray Nedalgi ,  Prasad Bhilawadi

IPC: G06K19/00 ,  H02H3/18 ,  G06F1/26 ,  G06F1/3212 ,  H04B1/38 ,  H04L25/02

Abstract: Described is an apparatus which comprises: one or more signal lines; a transceiver coupled to the one or more signal lines; and a bias generation circuit to provide one or more bias voltages for the transceiver to tri-state the transceiver according to signal attributes of the one or more signal lines.