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    DEVICE, METHOD, AND SYSTEM TO FACILITATE IMPROVED BANDWIDTH OF A BRANCH PREDICTION UNIT
    1.
    发明公开
    DEVICE, METHOD, AND SYSTEM TO FACILITATE IMPROVED BANDWIDTH OF A BRANCH PREDICTION UNIT 审中-公开

    公开(公告)号：US20230195469A1

    公开(公告)日：2023-06-22

    申请号：US17558361

    申请日：2021-12-21

    Applicant: Intel Corporation

    Inventor： Sumeet Bandishte ,  Jayesh Gaur ,  Franck Sala ,  Alexey Yurievich Sivtsov ,  Jared Warner Stark, IV ,  Lihu Rappoport ,  Sreenivas Subramoney

    IPC: G06F9/38

    CPC classification number: G06F9/3848 ,  G06F9/3867 ,  G06F9/3814

    Abstract: Techniques and mechanisms for a processor to determine an execution of instructions based on a prediction of a taken branch. In an embodiment, a first prediction unit generates each of multiple branch predictions in one cycle of successive branch prediction cycles. An indication of the branch predictions is provided to an execution pipeline, which prepares to execute an instruction based on the indication. Where a first one of the branch predictions is determined to be of a low confidence type, said first branch prediction is further indicated to a second prediction unit, which performs a second branch prediction based on the same branch instruction for which the first branch prediction was made. In another embodiment, the second prediction unit signals that a state of the execution pipeline is to be cleared, based on a determination that the first and second branch predictions are inconsistent with each other.

    Technology For Dynamically Tuning Processor Features
    2.
    发明申请
    Technology For Dynamically Tuning Processor Features 有权

    公开(公告)号：US20210109839A1

    公开(公告)日：2021-04-15

    申请号：US17128291

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Franck Sala ,  Lihu Rappoport ,  Zeev Sperber ,  Adi Yoaz ,  Sreenivas Subramoney

    IPC: G06F11/34 ,  G06F11/30 ,  G06F9/24 ,  G06F9/38 ,  G06F15/78

    Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

    System of improved loop detection and execution
    4.
    发明授权
    System of improved loop detection and execution 有权
    改进环路检测和执行系统

    公开(公告)号：US09459871B2

    公开(公告)日：2016-10-04

    申请号：US13731377

    申请日：2012-12-31

    Applicant: INTEL CORPORATION

    Inventor： Masha Lipshits ,  Lihu Rappaport ,  Shantanu Gupta ,  Franck Sala ,  Naveen Kumar ,  Allan D. Knies

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32

    CPC classification number: G06F9/30065 ,  G06F9/325 ,  G06F9/381 ,  G06F9/3844

    Abstract: A method, system, and computer program product for identifying loop information corresponding to a plurality of loop instructions. The loop instructions are stored into a queue. The loop instructions are replayed from the queue for execution. Loop iteration is counted based on the identified loop information. A determination is made of whether the last iteration of the loop is done. If the last iteration is not done, then embodiments continue replaying the loop instructions, until the last iteration is done.

    Abstract translation: 一种用于识别对应于多个循环指令的循环信息的方法，系统和计算机程序产品。 循环指令存储到队列中。 循环指令从队列中重播以供执行。 循环迭代根据识别的循环信息进行计数。 确定循环的最后一次迭代是否完成。 如果最后一次迭代未完成，则实施例继续重播循环指令，直到完成最后一次迭代。

    Technology for dynamically tuning processor features
    5.
    发明授权
    Technology for dynamically tuning processor features 有权

    公开(公告)号：US11656971B2

    公开(公告)日：2023-05-23

    申请号：US17582051

    申请日：2022-01-24

    Applicant: Intel Corporation

    Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Franck Sala ,  Lihu Rappoport ,  Zeev Sperber ,  Adi Yoaz ,  Sreenivas Subramoney

    IPC: G06F11/34 ,  G06F11/30 ,  G06F15/78 ,  G06F9/24 ,  G06F9/38

    CPC classification number: G06F11/3476 ,  G06F9/24 ,  G06F9/3836 ,  G06F11/3024 ,  G06F11/3055 ,  G06F15/7875

    Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

    Technology For Dynamically Tuning Processor Features
    6.
    发明申请
    Technology For Dynamically Tuning Processor Features 有权

    公开(公告)号：US20220206925A1

    公开(公告)日：2022-06-30

    申请号：US17582051

    申请日：2022-01-24

    Applicant: Intel Corporation

    Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Franck Sala ,  Lihu Rappoport ,  Zeev Sperber ,  Adi Yoaz ,  Sreenivas Subramoney

    IPC: G06F11/34 ,  G06F9/24 ,  G06F9/38 ,  G06F11/30 ,  G06F15/78

    Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

    Technology for dynamically tuning processor features
    7.
    发明授权
    Technology for dynamically tuning processor features 有权

    公开(公告)号：US10915421B1

    公开(公告)日：2021-02-09

    申请号：US16575535

    申请日：2019-09-19

    Applicant: Intel Corporation

    Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Franck Sala ,  Lihu Rappoport ,  Zeev Sperber ,  Adi Yoaz ,  Sreenivas Subramoney

    IPC: G06F11/34 ,  G06F15/78 ,  G06F11/30 ,  G06F9/38 ,  G06F9/24

    Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

    Technology for dynamically tuning processor features
    10.
    发明授权
    Technology for dynamically tuning processor features 有权

    公开(公告)号：US11256599B2

    公开(公告)日：2022-02-22

    申请号：US17128291

    申请日：2020-12-21

    Applicant: Intel Corporation

    Inventor： Adarsh Chauhan ,  Jayesh Gaur ,  Franck Sala ,  Lihu Rappoport ,  Zeev Sperber ,  Adi Yoaz ,  Sreenivas Subramoney

    IPC: G06F11/34 ,  G06F11/30 ,  G06F15/78 ,  G06F9/24 ,  G06F9/38

    Abstract: A processor comprises a microarchitectural feature and dynamic tuning unit (DTU) circuitry. The processor executes a program for first and second execution windows with the microarchitectural feature disabled and enabled, respectively. The DTU circuitry automatically determines whether the processor achieved worse performance in the second execution window. In response to determining that the processor achieved worse performance in the second execution window, the DTU circuitry updates a usefulness state for a selected address of the program to denote worse performance. In response to multiple consecutive determinations that the processor achieved worse performance with the microarchitectural feature enabled, the DTU circuitry automatically updates the usefulness state to denote a confirmed bad state. In response to the usefulness state denoting the confirmed bad state, the DTU circuitry automatically disables the microarchitectural feature for the selected address for execution windows after the second execution window. Other embodiments are described and claimed.

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