公开(公告)号：US20240078630A1

公开(公告)日：2024-03-07

申请号：US18490593

申请日：2023-10-19

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Durgaprasad Bilagi ,  Joydeep Ray ,  Scott Janus ,  Sanjeev Jahagirdar ,  Brent Insko ,  Lidong Xu ,  Abhishek R. Appu ,  James Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Xinmin Tian ,  Guei-Yuan Lueh ,  Changliang Wang

IPC: G06T1/60 ,  G06F12/0802 ,  G06N5/04 ,  G06T1/20

CPC classification number: G06T1/60 ,  G06F12/0802 ,  G06N5/04 ,  G06T1/20 ,  G06F2212/251

Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

公开(公告)号：US11663746B2

公开(公告)日：2023-05-30

申请号：US17095544

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Prasoonkumar Surti ,  Jill Boyce ,  Subramaniam Maiyuran ,  Michael Apodaca ,  Adam T. Lake ,  James Holland ,  Vasanth Ranganathan ,  Altug Koker ,  Lidong Xu ,  Nikos Kaburlasos

IPC: G06T9/00 ,  G06T15/00 ,  G06N3/045

CPC classification number: G06T9/002 ,  G06N3/045 ,  G06T9/007 ,  G06T9/008 ,  G06T15/005

Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.

公开(公告)号：US12147302B2

公开(公告)日：2024-11-19

申请号：US17095530

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Joydeep Ray ,  Abhishek R. Appu ,  Nikos Kaburlasos ,  Lidong Xu ,  Subramaniam Maiyuran ,  Altug Koker ,  Naveen Matam ,  James Holland ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Durgaprasad Bilagi ,  Xinmin Tian

IPC: G06F11/10 ,  G06F12/0802 ,  G06T1/20 ,  G06T1/60

Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

公开(公告)号：US12101475B2

公开(公告)日：2024-09-24

申请号：US17127544

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Brinda Ganesh ,  Nilesh Jain ,  Sumit Mohan ,  Faouzi Kossentini ,  Jill Boyce ,  James Holland ,  Zhijun Lei ,  Chekib Nouira ,  Foued Ben Amara ,  Hassene Tmar ,  Sebastian Possos ,  Craig Hurst

IPC: H04N19/114 ,  H04N19/154

CPC classification number: H04N19/114 ,  H04N19/154

Abstract: Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.

公开(公告)号：US11729403B2

公开(公告)日：2023-08-15

申请号：US16647998

申请日：2017-12-05

Applicant: INTEL CORPORATION

Inventor： James Holland ,  Hiu-Fai Chan ,  Fangwen Fu ,  Qian Xu ,  Sang-Hee Lee ,  Vidhya Krishnan

IPC: H04N11/02 ,  H04N19/182 ,  H04N19/423

CPC classification number: H04N19/182 ,  H04N19/423

Abstract: A lossless pixel compressor may include technology to detect a format of a pixel memory region, and compress the pixel memory region together with embedded control information which indicates the detected format of the pixel memory region. Other embodiments are disclosed and claimed.

公开(公告)号：US20210150663A1

公开(公告)日：2021-05-20

申请号：US17095590

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Durgaprasad Bilagi ,  Joydeep Ray ,  Scott Janus ,  Sanjeev Jahagirdar ,  Brent Insko ,  Lidong Xu ,  Abhishek R. Appu ,  James Holland ,  Vasanth Ranganathan ,  Nikos Kaburlasos ,  Altug Koker ,  Xinmin Tian ,  Guei-Yuan Lueh ,  Changliang Wang

IPC: G06T1/60 ,  G06T1/20 ,  G06N5/04 ,  G06F12/0802

Abstract: Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

公开(公告)号：US20250103430A1

公开(公告)日：2025-03-27

申请号：US18907092

申请日：2024-10-04

Applicant: Intel Corporation

Inventor： Vasanth Ranganathan ,  Joydeep Ray ,  Abhishek R. Appu ,  Nikos Kaburlasos ,  Lidong Xu ,  Subramaniam Maiyuran ,  Altug Koker ,  Naveen Matam ,  James Holland ,  Brent Insko ,  Sanjeev Jahagirdar ,  Scott Janus ,  Durgaprasad Bilagi ,  Xinmin Tian

IPC: G06F11/10 ,  G06F12/0802 ,  G06T1/20 ,  G06T1/60

Abstract: Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

公开(公告)号：US20250055987A1

公开(公告)日：2025-02-13

申请号：US18812760

申请日：2024-08-22

Applicant: Intel Corporation

Inventor： Brinda Ganesh ,  Nilesh Jain ,  Sumit Mohan ,  Faouzi Kossentini ,  Jill Boyce ,  James Holland ,  Zhijun Lei ,  Chekib Nouira ,  Foued Ben Amara ,  Hassene Tmar ,  Sebastian Possos ,  Craig Hurst

IPC: H04N19/114 ,  H04N19/154

Abstract: Techniques related to distributing the video encoding processing of an input video across hardware and software systems. Such techniques include evaluating the content of the video and determine whether or the encoding operation is best to be done on the hardware system only, software system only or a hybrid hardware and software system.

公开(公告)号：US20240331168A1

公开(公告)日：2024-10-03

申请号：US18309534

申请日：2023-04-28

Applicant: Intel Corporation

Inventor： James Holland ,  Muhammad Hamdan ,  Timothy Chong ,  Lidong Xu ,  Yang Zhou

IPC: G06T7/246

CPC classification number: G06T7/248 ,  G06T2207/10016 ,  G06T2207/20084

Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to determine confidence of motion vectors. Examples disclosed herein are to generate feature data associated with a motion vector, the motion vector generated based on a first block of pixel data in a first video frame and a second block of pixel data in a second video frame, determine a confidence score for the motion vector based on a model and the feature data, and concatenate the motion vector and the confidence score to output an estimated likelihood that the motion vector is accurate.

公开(公告)号：US20230412808A1

公开(公告)日：2023-12-21

申请号：US18031563

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： James Holland ,  Sang-hee Lee ,  Ximin Zhang ,  Zhan Lou

IPC: H04N19/126 ,  H04N19/149 ,  H04N19/172 ,  G06N20/00

CPC classification number: H04N19/126 ,  G06N20/00 ,  H04N19/172 ,  H04N19/149

Abstract: Techniques related to adaptive quantization matrix selection using machine learning for video coding are discussed. Such techniques include applying a machine learning model to generate an estimated quantization parameter for a frame and selecting a set of quantization matrices for encode of the frame from a number of sets of quantization matrices based on the estimated quantization parameter.