公开(公告)号：US11543868B2

公开(公告)日：2023-01-03

申请号：US16898603

申请日：2020-06-11

Applicant: Intel Corporation

Inventor： Tessil Thomas ,  Robin A. Steinbrecher ,  Sandeep Ahuja ,  Michael Berktold ,  Timothy Y. Kam ,  Howard Chin ,  Phani Kumar Kandula ,  Krishnakanth V. Sistla

IPC: G06F1/20 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  G06F3/041 ,  G06F11/30 ,  G06F1/32 ,  G06F1/26

Abstract: In an embodiment, a processor includes at least one core and power management logic. The power management logic is to receive temperature data from a plurality of dies within a package that includes the processor, and determine a smallest temperature control margin of a plurality of temperature control margins. Each temperature control margin is to be determined based on a respective thermal control temperature associated with the die and also based on respective temperature data associated with the die. The power management logic is also to generate a thermal report that is to include the smallest temperature control margin, and to store the thermal report. Other embodiments are described and claimed.

公开(公告)号：US20220197361A1

公开(公告)日：2022-06-23

申请号：US17563605

申请日：2021-12-28

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Nir Rosenzweig ,  Krishnakanth V. Sistla ,  Ashish V. Choubal ,  Ankush Varma

IPC: G06F1/324 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/26

Abstract: Apparatuses, methods and storage medium associated with current control for a multicore processor are disclosed herein. In embodiments, a multicore processor may include a plurality of analog current comparators, each analog current comparator to measure current utilization by a corresponding one of the cores of the multicore processor. The multicore processor may include one or more processors, devices, and/or circuitry to cause the cores to individually throttle based on measurements from the corresponding analog current comparators. In some embodiments, a memory device of the multicore processor may store instructions executable to operate a plurality power management agents to determine whether to send throttle requests based on a plurality of histories of the current measurements of the cores, respectively.

公开(公告)号：US20220129031A1

公开(公告)日：2022-04-28

申请号：US17520296

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US11294749B2

公开(公告)日：2022-04-05

申请号：US15859474

申请日：2017-12-30

Applicant: Intel Corporation

Inventor： Ramamurthy Krithivas ,  Anand K. Enamandram ,  Eswaramoorthi Nallusamy ,  Russell J. Wunderlich ,  Krishnakanth V. Sistla

IPC: G06F11/07

Abstract: Examples include techniques to collect crash data for a computing system following a catastrophic error. Examples include a management controller gathering error information from components of a computing system that includes a central processing unit (CPU) coupled with one or more companion dice following the catastrophic error. The management controller to gather the error information via a communication link coupled between the management controller, the CPU and the one or more companion dice.

公开(公告)号：US11256657B2

公开(公告)日：2022-02-22

申请号：US16364619

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Tejpal Singh ,  Yedidya Hilewitz ,  Ankush Varma ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Jeffrey Chamberlain

IPC: G06F15/00 ,  G06F15/76 ,  G06F15/78 ,  G06F9/54 ,  G06F9/30 ,  G06F1/3296 ,  G06F1/3234

Abstract: In one embodiment, an apparatus includes an interconnect to couple a plurality of processing circuits. The interconnect may include a pipe stage circuit coupled between a first processing circuit and a second processing circuit. This pipe stage circuit may include: a pipe stage component having a first input to receive a signal via the interconnect and a first output to output the signal; and a selection circuit having a first input to receive the signal from the first output of the pipe stage component and a second input to receive the signal via a bypass path, where the selection circuit is dynamically controllable to output the signal received from the first output of the pipe stage component or the signal received via the bypass path. Other embodiments are described and claimed.

公开(公告)号：US20190317773A1

公开(公告)日：2019-10-17

申请号：US16388670

申请日：2019-04-18

Applicant: Intel Corporation

Inventor： Guy M. Therien ,  Paul S. Diefenbaugh ,  Anil Aggarwal ,  Andrew D. Henroid ,  Jeremy J. Shrall ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Eliezer Weissmann

IPC: G06F9/4401 ,  G06F16/22 ,  G06F1/324 ,  G06F1/3234 ,  G06F9/44 ,  G06F1/26 ,  G06F9/22 ,  G06F9/445 ,  G06F11/36 ,  G06F1/3203 ,  G06F11/34 ,  G06F11/30 ,  G06F1/3296 ,  G06F1/28

Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.

公开(公告)号：US10310588B2

公开(公告)日：2019-06-04

申请号：US15296096

申请日：2016-10-18

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Allen W. Chu ,  Ian M. Steiner

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/48

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.

公开(公告)号：US20180173298A1

公开(公告)日：2018-06-21

申请号：US15381611

申请日：2016-12-16

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Boris Mishori ,  Krishnakanth V. Sistla ,  Ankush Varma ,  Avinash N. Ananthakrishnan ,  Lev Makovsky ,  Michael Zelikson ,  Eran Altshuler ,  Israel Stolero

IPC: G06F1/32 ,  G06F1/20 ,  G06F1/04

CPC classification number: G06F1/3296 ,  G06F1/206 ,  G06F1/3206 ,  G06F1/324

Abstract: An apparatus is provided, comprising: a first circuitry configured to generate a signal at a voltage level for one or more components; a second circuitry configured to generate a clock at a frequency level for the one or more components; a third circuitry configured to intermittently measure a current level of the signal; a fourth circuitry configured to estimate a first average of the current level of the signal over a first time-window; and a fifth circuitry configured to, in response to the first average being higher than a threshold average current, facilitate regulating one or both the voltage level of the signal or the frequency level of the clock.

公开(公告)号：US09841997B2

公开(公告)日：2017-12-12

申请号：US14750212

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Kristoffer D. Fleming ,  Eugene Gorbatov ,  Robert E. Gough ,  Krishnakanth V. Sistla

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/455

CPC classification number: G06F9/4893 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/455

Abstract: An apparatus and method for performing high performance instruction emulation. One embodiment of the invention includes a processor to process an instruction set including high-power and standard instructions comprising: an analysis module to determine whether a number of high-power instructions within a specified window are above or below a specified threshold; an execution mode selection module to select a native execution of the high-power instructions if the number of high-power instructions are above the specified threshold or to select an emulated execution of the high-power instructions if the number of high-power instructions are below the specified threshold.

公开(公告)号：US09720491B2

公开(公告)日：2017-08-01

申请号：US14752841

申请日：2015-06-27

Applicant: Intel Corporation

Inventor： Dean Mulla ,  Daniel G. Borkowski ,  Krishnakanth V. Sistla ,  Victor Wu ,  Manev Luthra

IPC: G06F3/06 ,  G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/3225 ,  G06F1/3237 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0673 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/172

Abstract: Systems and methods may provide for determining, in a first domain that manages a state of a second domain, that the second domain is in the state and determining, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state. Additionally, the periodic action may be documented as a missed event with respect to the second domain. In one example, documenting the periodic action as a missed event includes incrementing a missed event counter.