公开(公告)号：US20220256715A1

公开(公告)日：2022-08-11

申请号：US17390601

申请日：2021-07-30

Applicant: Intel Corporation

Inventor： Divya MANI ,  William J. LAMBERT ,  Shawna LIFF ,  Sergio A. CHAN ARGUEDAS ,  Robert L. SANKMAN

IPC: H05K3/34

Abstract: Embodiments of the invention include a mmWave transceiver and methods of forming such devices. In an embodiment, the mmWave transceiver includes an RF module. The RF module may include a package substrate, a plurality of antennas formed on the package substrate, and a die attached to a surface of the package substrate. In an embodiment, the mmWave transceiver may also include a mainboard mounted to the RF module with one or more solder balls. In an embodiment, a thermal feature is embedded within the mainboard, and the thermal feature is separated from the die by a thermal interface material (TIM) layer. According to an embodiment, the thermal features are slugs and/or vias. In an embodiment, the die compresses the TIM layer resulting in a TIM layer with minimal thickness.

公开(公告)号：US20240038687A1

公开(公告)日：2024-02-01

申请号：US18380022

申请日：2023-10-13

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Shawna LIFF ,  Srinivas PIETAMBARAM ,  Bharat PENMECHA

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US20230134049A1

公开(公告)日：2023-05-04

申请号：US18089227

申请日：2022-12-27

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Shawna LIFF ,  Srinivas PIETAMBARAM ,  Bharat PENMECHA

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US20200065263A1

公开(公告)日：2020-02-27

申请号：US15746792

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Shawna LIFF ,  Adel A. ELSHERBINI ,  Telesphor KAMGAING ,  Sasha N. OSTER ,  Gaurav CHAWLA

IPC: G06F13/14 ,  G02B6/42 ,  H04M9/06 ,  H01P5/00 ,  H01Q13/10 ,  H04B1/40 ,  H04B7/00

Abstract: Microelectronic package communication is described using radio interfaces connected through wiring. One example includes a system board, an integrated circuit chip, and a package substrate mounted to the system board to carry the integrated circuit chip, the package substrate having conductive connectors to connect the integrated circuit chip to external components. A radio on the package substrate is coupled to the integrated circuit chip to modulate the data onto a carrier and to transmit the modulated data. A radio on the system board receives the transmitted modulated data and demodulates the received data, and a cable interface is coupled to the system board radio to couple the received demodulated data to a cable.

公开(公告)号：US20240128205A1

公开(公告)日：2024-04-18

申请号：US18397915

申请日：2023-12-27

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Ravindranath MAHAJAN ,  Robert SANKMAN ,  Shawna LIFF ,  Srinivas PIETAMBARAM ,  Bharat PENMECHA

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/5381 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/3511

Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.

公开(公告)号：US20200051899A1

公开(公告)日：2020-02-13

申请号：US16059535

申请日：2018-08-09

Applicant: Intel Corporation

Inventor： Debendra MALLIK ,  Sanka GANESAN ,  Pilin LIU ,  Shawna LIFF ,  Sri Chaitra CHAVALI ,  Sandeep GAAN ,  Jimin YAO ,  Aastha UPPAL

IPC: H01L23/498 ,  H01L23/28 ,  H01L23/34 ,  H01L23/538 ,  H01L23/532

Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

公开(公告)号：US20170079135A1

公开(公告)日：2017-03-16

申请号：US15123215

申请日：2014-05-28

Applicant: INTEL CORPORATION

Inventor： Chuan HU ,  Adel A. ELSHERBINI ,  Yoshihiro TOMITA ,  Shawna LIFF

IPC: H05K1/02 ,  H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/31

CPC classification number: H05K1/0283 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/1515 ,  H01L2924/181 ,  H05K1/036 ,  H05K1/185 ,  H05K3/1275 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/09018 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09263 ,  H05K2201/10151 ,  H01L2924/00012

Abstract: Embodiments of the present disclosure describe a wavy interconnect for bendable and stretchable devices and associated techniques and configurations. In one embodiment, an interconnect assembly includes a flexible substrate defining a plane and a wavy interconnect disposed on the flexible substrate and configured to route electrical signals of an integrated circuit (IC) device in a first direction that is coplanar with the plane, the wavy interconnect having a wavy profile from a second direction that is perpendicular to the first direction and coplanar with the plane. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了用于可弯曲和可拉伸装置的波浪互连以及相关技术和配置。 在一个实施例中，互连组件包括限定平面的柔性衬底和布置在柔性衬底上的波纹互连，并且被配置成沿与平面共面的第一方向布置集成电路（IC）器件的电信号，波形 互连件具有从垂直于第一方向并与该平面共面的第二方向的波状轮廓。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20230130935A1

公开(公告)日：2023-04-27

申请号：US18088476

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Adel ELSHERBINI ,  Mauro KOBRINSKY ,  Shawna LIFF ,  Johanna SWAN ,  Gerald PASDAST ,  Sathya Narasimman TIAGARAJ

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

公开(公告)号：US20210041647A1

公开(公告)日：2021-02-11

申请号：US17083173

申请日：2020-10-28

Applicant: Intel Corporation

Inventor： Shawna LIFF ,  Adel A. ELSHERBINI ,  Telesphor KAMGAING ,  Sasha N. OSTER ,  Gaurav CHAWLA

IPC: G02B6/42

Abstract: Microelectronic package communication is described using radio interfaces connected through wiring. One example includes a system board, an integrated circuit chip, and a package substrate mounted to the system board to carry the integrated circuit chip, the package substrate having conductive connectors to connect the integrated circuit chip to external components. A radio on the package substrate is coupled to the integrated circuit chip to modulate the data onto a carrier and to transmit the modulated data. A radio on the system board receives the transmitted modulated data and demodulates the received data, and a cable interface is coupled to the system board radio to couple the received demodulated data to a cable.

公开(公告)号：US20200312803A1

公开(公告)日：2020-10-01

申请号：US16363996

申请日：2019-03-25

Applicant: Intel Corporation

Inventor： Jimin YAO ,  Shawna LIFF ,  Xin YAN ,  Numair AHMED

IPC: H01L23/00

Abstract: Embodiments herein relate to systems, apparatuses, or processes directed to an interconnect joint that includes multiple core balls within a solder compound where the multiple core balls are substantially linearly aligned. The multiple core balls, which may include copper or be a polymer, couple with each other within the solder and form a substantially linear alignment during reflow. In embodiments, four or more core balls may be used to achieve a high aspect ratio interconnect joint with a tight pitch.