公开(公告)号：US09753510B2

公开(公告)日：2017-09-05

申请号：US14836780

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Srikrishnan Venkataraman ,  William J. Lambert ,  Michael J. Hill ,  Alexander Slepoy ,  Dong Zhong ,  Kaladhar Radhakrishnan ,  Hector A. Aguirre Diaz ,  Jonathan P. Douglas

IPC: G06F1/26 ,  G06F1/32 ,  H02J1/00 ,  H02M3/158 ,  H02M1/00

CPC classification number: G06F1/26 ,  G06F1/3203 ,  H01L23/645 ,  H02J1/00 ,  H02M3/158 ,  H02M3/1584 ,  H02M2001/008 ,  H02M2003/1586

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

公开(公告)号：US11372467B2

公开(公告)日：2022-06-28

申请号：US16914290

申请日：2020-06-27

Applicant: Intel Corporation

Inventor： Ahmed Abou-Alfotouh ,  Phani Kumar Kandula ,  Linda L. Hurd ,  Eric C. Samson ,  Srikrishnan Venkataraman

IPC: G06F1/32 ,  G06F1/3234

Abstract: A system includes multiple processors and a power controller. Each processor includes a throttling engine. The power controller is to, in response to a determination that a first power consumption level exceeds a first threshold, assert a critical signal to each throttling engine of the plurality of processors. Further, for each processor, the throttling engine of the processor is to perform a sequence of multiple throttling states while the critical signal is asserted by the power controller, where the sequence of multiple throttling states is performed according to a state machine of the throttling engine. Other embodiments are described and claimed.

公开(公告)号：US10122209B1

公开(公告)日：2018-11-06

申请号：US15628375

申请日：2017-06-20

Applicant: Intel Corporation

Inventor： Ahmed Fouad Salama ,  Srikrishnan Venkataraman ,  Todd W. Mellinger ,  Michael J. Hill ,  Paul K. Tucker ,  Assaf Benhamou

IPC: G05F1/00 ,  G05F1/565 ,  H02J13/00 ,  H02J3/06 ,  B06B1/02 ,  H02J5/00 ,  H02J50/80 ,  H04J14/02

Abstract: An apparatus system is provided which comprises: a first component to receive a first signal via a first delay circuit; a second component to receive a second signal via a second delay circuit; and one or more circuitries to tune a first delay of the first delay circuit and a second delay of the second delay circuit, based at least in part on monitoring of a voltage level.

公开(公告)号：US12007828B2

公开(公告)日：2024-06-11

申请号：US17628886

申请日：2020-08-03

Applicant: Intel Corporation

Inventor： Srikrishnan Venkataraman ,  Mallari Hanchate ,  Sayan Lahiri ,  Vijayakumar Dibbad

IPC: G06F1/3293 ,  G06F9/50 ,  G06T1/20

CPC classification number: G06F1/3293 ,  G06F9/5094 ,  G06T1/20

Abstract: A switchable graphics management scheme, which uses performance/watt information of both the iGPU/dGPU along with system real-time resources like SoC (system-on-chip) thermal, system power budgets to decide on the right GPU for rendering tasks. The scheme uses this threshold power point information along with system resources to determine the optimized GPU for tasks rendering for all applications and use cases. As such, the scheme of adapts to each system design based on capabilities of that specific system.

公开(公告)号：US20170060205A1

公开(公告)日：2017-03-02

申请号：US14836780

申请日：2015-08-26

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Srikrishnan Venkataraman ,  William J. Lambert ,  Michael J. Hill ,  Alexander Slepoy ,  Dong Zhong ,  Kaladhar Radhakrishnan ,  Hector A. Aguirre Diaz ,  Jonathan P. Douglas

IPC: G06F1/26 ,  H02J1/00 ,  G06F1/32 ,  H02M3/158

CPC classification number: G06F1/26 ,  G06F1/3203 ,  H01L23/645 ,  H02J1/00 ,  H02M3/158 ,  H02M3/1584 ,  H02M2001/008 ,  H02M2003/1586

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.

Abstract translation: 描述了一种装置，其包括：耦合到第一一个或多个电感器的第一电压调节器（VR），第一VR为第一功率域提供电力; 以及耦合到第二一个或多个电感器的第二VR，其中至少一个电感器感应耦合到所述第一个或多个电感器中的至少一个，所述第二VR为与所述第一电源域分离的第二电力域提供电力， 其中在第一VR相对于第二VR的开关晶体管之间存在非零相位角偏移。

公开(公告)号：US10404152B2

公开(公告)日：2019-09-03

申请号：US15721314

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Srikrishnan Venkataraman ,  Sreedhar Narayanaswamy ,  Jonathan P. Douglas ,  Chih-Chung Jonathan Wei ,  Ankush Varma ,  Narayanan Natarajan

IPC: H02M1/00 ,  G06F1/26 ,  H03L7/099

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit device. Each of the voltage regulators includes a current sensor. The frequency control block operates to provide a clock signal to each of the voltage regulators. The clock signal has a frequency based on digital information. The module operates to receive a current from the current sensor of each of the voltage regulators and provides the digital information to the frequency control block to control the frequency of the clock signal. The digital information has a value based on the current from each of the current sensors.

公开(公告)号：US20190103801A1

公开(公告)日：2019-04-04

申请号：US15721314

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Srikrishnan Venkataraman ,  Sreedhar Narayanaswamy ,  Jonathan P. Douglas ,  Chih-Chung Jonathan Wei ,  Ankush Varma ,  Narayanan Natarajan

IPC: H02M1/00 ,  G06F1/26

CPC classification number: H02M1/00 ,  G06F1/26 ,  H02M3/158 ,  H02M3/33561 ,  H02M2001/0009 ,  H02M2001/0012 ,  H02M2001/008 ,  H03L7/099

Abstract: Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes voltage regulators in an integrated circuit device, and a frequency control block and a module included in the integrated circuit device. Each of the voltage regulators includes a current sensor. The frequency control block operates to provide a clock signal to each of the voltage regulators. The clock signal has a frequency based on digital information. The module operates to receive a current from the current sensor of each of the voltage regulators and provides the digital information to the frequency control block to control the frequency of the clock signal. The digital information has a value based on the current from each of the current sensors.

公开(公告)号：US20180101207A1

公开(公告)日：2018-04-12

申请号：US15695947

申请日：2017-09-05

Applicant: INTEL CORPORATION

Inventor： Krishna Bharath ,  Srikrishnan Venkataraman ,  William J. Lambert ,  Michael J. Hill ,  Alexander Slepoy ,  Dong Zhong ,  Kaladhar Radhakrishnan ,  Hector A. Aguirre Diaz ,  Jonathan P. Douglas

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3203 ,  H01L23/645 ,  H02J1/00 ,  H02M1/14 ,  H02M3/158 ,  H02M3/1584 ,  H02M2001/008 ,  H02M2003/1586

Abstract: Described is an apparatus which comprises: a first voltage regulator (VR) coupled to first one or more inductors, the first VR is to provide power to a first power domain; and a second VR coupled to second one or more inductors at least one of which is inductively coupled to at least one of the first one or more inductors, the second VR is to provide power to a second power domain separate from the first power domain, wherein there is a non-zero phase angle offset between switching transistors of the first VR relative to the second VR.